添加aio-3399b的支持
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@ -8,10 +8,18 @@ PKG_NAME:=arm-trusted-firmware-rockchip-vendor
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PKG_RELEASE:=$(AUTORELEASE)
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PKG_SOURCE_PROTO:=git
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ifeq ($(HOST_ARCH),aarch64)
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PKG_SOURCE_VERSION:=9f843531d8dae25772efff7590908e974cf48540
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PKG_MIRROR_HASH:=7699938adb7d5fe4f73aacd8082b497dca3eb288d6198edeb86209d14b5d83d7
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PKG_SOURCE_URL=http://gits.kos.org.cn:3000/k/rkbin.git
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PKG_SOURCE_DATE:=2023-05-31
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else
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PKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git
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PKG_SOURCE_DATE:=2023-07-26
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PKG_SOURCE_VERSION:=b4558da0860ca48bf1a571dd33ccba580b9abe23
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PKG_MIRROR_HASH:=50e904a9d53466449155ff8f80522ffdfe7fb36a2ff13055416259e1468c07bf
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endif
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PKG_MAINTAINER:=Tianling Shen <cnsztl@immortalwrt.org>
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@ -135,6 +135,17 @@ define U-Boot/rongpin-king3399-rk3399
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USE_RKBIN:=1
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endef
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define U-Boot/aio-3399b-rk3399
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BUILD_SUBTARGET:=armv8
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DEPENDS:=+PACKAGE_u-boot-aio-3399b-rk3399:arm-trusted-firmware-rk3399
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3399_bl31_v1.36.elf
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USE_RKBIN:=1
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NAME:=AIO-3399B
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BUILD_DEVICES:= \
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aio-3399b
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endef
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define U-Boot/rocktech-mpc1903-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=Rocktech MPC1903
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@ -312,6 +323,7 @@ UBOOT_TARGETS := \
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guangmiao-g4c-rk3399 \
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nanopi-r4s-rk3399 \
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nanopi-r4se-rk3399 \
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aio-3399b-rk3399 \
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nanopi-r5s-rk3568 \
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rock-pi-4-rk3399 \
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rockpro64-rk3399 \
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@ -0,0 +1,10 @@
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -166,6 +166,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
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rk3399-rock-pi-4c.dtb \
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rk3399-rock960.dtb \
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rk3399-mpc1903.dtb \
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+ rk3399-aio-3399b.dtb \
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rk3399-rockpro64.dtb \
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rk3399pro-rock-pi-n10.dtb
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@ -0,0 +1,14 @@
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// SPDX-License-Identifier: GPL-2.0
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#include "rk3399-u-boot.dtsi"
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#include "rk3399-sdram-ddr3-1600.dtsi"
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#include "rk3399-sdram-lpddr4-100.dtsi"
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/ {
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chosen {
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u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
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};
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};
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&vdd_log {
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regulator-init-microvolt = <950000>;
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};
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,92 @@
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CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_TEXT_BASE=0x00200000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
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CONFIG_ENV_OFFSET=0x3F8000
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CONFIG_DEFAULT_DEVICE_TREE="rk3399-aio-3399b"
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CONFIG_DM_RESET=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_TARGET_EVB_RK3399=y
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CONFIG_SPL_STACK=0x400000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SYS_LOAD_ADDR=0x800800
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CONFIG_PCI=y
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CONFIG_DEBUG_UART=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-aio-3399b.dtb"
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_MISC_INIT_R=y
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CONFIG_SPL_MAX_SIZE=0x2e000
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CONFIG_SPL_PAD_TO=0x7f8000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x400000
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CONFIG_SPL_BSS_MAX_SIZE=0x2000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
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CONFIG_TPL=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_TIME=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MISC=y
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CONFIG_ROCKCHIP_EFUSE=y
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CONFIG_ROCKCHIP_OTP=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_SF_DEFAULT_SPEED=20000000
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_NVME_PCI=y
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CONFIG_PCI=y
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CONFIG_RAM_RK3399_LPDDR4=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_REGULATOR_PWM=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_RAM_ROCKCHIP_LPDDR4=y
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CONFIG_DM_RNG=y
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CONFIG_RNG_ROCKCHIP=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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CONFIG_SYSINFO=y
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CONFIG_SYSINFO_SMBIOS=y
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CONFIG_SYSRESET=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_KEYBOARD=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GENERIC=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_ASIX88179=y
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CONFIG_USB_ETHER_MCS7830=y
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CONFIG_USB_ETHER_RTL8152=y
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CONFIG_USB_ETHER_SMSC95XX=y
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CONFIG_USB_GADGET=y
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CONFIG_VIDEO=y
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CONFIG_DISPLAY=y
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CONFIG_VIDEO_ROCKCHIP=y
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CONFIG_DISPLAY_ROCKCHIP_HDMI=y
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CONFIG_SPL_TINY_MEMSET=y
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CONFIG_ERRNO_STR=y
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@ -144,3 +144,15 @@ define Package/panther-x2-firmware/install
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$(INSTALL_DATA) ./brcm_firmware/ap6236/brcmfmac43430-sdio.txt $(1)/lib/firmware/brcm/brcmfmac43430-sdio.txt
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endef
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$(eval $(call BuildPackage,panther-x2-firmware))
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Package/aio-3399b-firmware = $(call Package/firmware-default,Broadcom FullMac SDIO firmware)
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define Package/aio-3399b-firmware/install
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$(INSTALL_DIR) $(1)/lib/firmware/brcm
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$(INSTALL_DATA) ./brcm_firmware/ap6356s/brcmfmac4356-sdio.rongpin,king3399.bin $(1)/lib/firmware/brcm/brcmfmac4356-sdio.aio,aio-3399b.bin
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$(INSTALL_DATA) ./brcm_firmware/ap6356s/brcmfmac4356-sdio.rongpin,king3399.txt $(1)/lib/firmware/brcm/brcmfmac4356-sdio.aio,aio-3399b.txt
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$(INSTALL_DATA) ./brcm_firmware/ap6275s/BCM4362A2.hcd $(1)/lib/firmware/brcm/BCM4362A2.hcd
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$(INSTALL_DATA) ./brcm_firmware/ap6275s/clm_bcm43752a2_ag.blob $(1)/lib/firmware/brcm/brcmfmac43752-sdio.clm_blob
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$(INSTALL_DATA) ./brcm_firmware/ap6275s/fw_bcm43752a2_ag_apsta.bin $(1)/lib/firmware/brcm/brcmfmac43752-sdio.aio,aio-3399b.bin
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$(INSTALL_DATA) ./brcm_firmware/ap6275s/nvram_ap6275s.txt $(1)/lib/firmware/brcm/brcmfmac43752-sdio.aio,aio-3399b.txt
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endef
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$(eval $(call BuildPackage,aio-3399b-firmware))
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@ -432,7 +432,7 @@ define KernelPackage/brcmfmac/config
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default y if TARGET_bcm27xx
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default y if TARGET_sunxi
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default y if TARGET_rockchip
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default n
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default y
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help
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Enable support for cards attached to an SDIO bus.
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Select this option only if you are sure that your
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@ -256,7 +256,7 @@ static int __rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
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int __rtl8366_mdio_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
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{
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u32 phy_id = MDC_REALTEK_PHY_ADDR;
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u32 phy_id = smi->phy_id ? smi->phy_id : MDC_REALTEK_PHY_ADDR;
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struct mii_bus *mbus = smi->ext_mbus;
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BUG_ON(in_interrupt());
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@ -293,7 +293,7 @@ int __rtl8366_mdio_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
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static int __rtl8366_mdio_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
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{
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u32 phy_id = MDC_REALTEK_PHY_ADDR;
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u32 phy_id = smi->phy_id ? smi->phy_id : MDC_REALTEK_PHY_ADDR;
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struct mii_bus *mbus = smi->ext_mbus;
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BUG_ON(in_interrupt());
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@ -64,6 +64,7 @@ struct rtl8366_smi {
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u8 dbg_vlan_4k_page;
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#endif
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struct mii_bus *ext_mbus;
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u32 phy_id;
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};
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struct rtl8366_vlan_mc {
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@ -213,6 +213,23 @@
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#define RTL8367B_RTL_MAGIC_ID_REG 0x13c2
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#define RTL8367B_RTL_MAGIC_ID_VAL 0x0249
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#define RTL8367S_EXT_TXC_DLY_REG 0x13f9
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#define RTL8367S_EXT1_GMII_TX_DELAY_SHIFT 12
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#define RTL8367S_EXT0_GMII_TX_DELAY_SHIFT 9
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#define RTL8367S_EXT_GMII_TX_DELAY_MASK GENMASK(2,0)
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#define RTL8367S_SDS_MISC 0x1d11
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#define RTL8367S_CFG_SGMII_RXFC BIT(14)
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#define RTL8367S_CFG_SGMII_TXFC BIT(13)
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#define RTL8367S_CFG_MAC8_SEL_HSGMII_SHIFT 11
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#define RTL8367S_CFG_MAC8_SEL_HSGMII_MASK BIT(11)
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#define RTL8367S_CFG_SGMII_FDUP BIT(10)
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#define RTL8367S_CFG_SGMII_LINK BIT(9)
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#define RTL8367S_CFG_SGMII_SPD_SHIFT 7
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#define RTL8367S_CFG_SGMII_SPD_MASK GENMASK(8,7)
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#define RTL8367S_CFG_MAC8_SEL_SGMII BIT(6)
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#define RTL8367B_IA_CTRL_REG 0x1f00
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#define RTL8367B_IA_CTRL_RW(_x) ((_x) << 1)
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#define RTL8367B_IA_CTRL_RW_READ RTL8367B_IA_CTRL_RW(0)
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@ -230,9 +247,18 @@
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#define RTL8367B_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r))
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/* SerDes indirect access */
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#define RTL8367S_SDS_INDACS_CMD_REG 0x6600
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#define RTL8367S_SDS_CMD BIT(7)
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#define RTL8367S_SDS_RWOP BIT(6)
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#define RTL8367S_SDS_INDACS_ADDR_REG 0x6601
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#define RTL8367S_SDS_INDACS_DATA_REG 0x6602
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#define RTL8367B_NUM_MIB_COUNTERS 58
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#define RTL8367S_PHY_ADDR 29
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#define RTL8367B_CPU_PORT_NUM 5
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#define RTL8367S_CPU_PORT_NUM 7
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#define RTL8367B_NUM_PORTS 8
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#define RTL8367B_NUM_VLANS 32
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#define RTL8367B_NUM_VIDS 4096
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@ -255,14 +281,16 @@
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#define RTL8367B_PORTS_ALL_BUT_CPU \
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(RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
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RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 | \
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RTL8367B_PORT_E2)
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RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 | \
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RTL8367B_PORT_E1)
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struct rtl8367b_initval {
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u16 reg;
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u16 val;
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};
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u32 rtl_device_id;
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#define RTL8367B_MIB_RXB_ID 0 /* IfInOctets */
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#define RTL8367B_MIB_TXB_ID 28 /* IfOutOctets */
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@ -605,6 +633,45 @@ static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {
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{0x133E, 0x000E}, {0x133F, 0x0010},
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};
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static const struct rtl8367b_initval rtl8367c_initvals0[] = {
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{0x13c2, 0x0000}, {0x0018, 0x0f00}, {0x0038, 0x0f00}, {0x0058, 0x0f00},
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{0x0078, 0x0f00}, {0x0098, 0x0f00}, {0x1d15, 0x0a69}, {0x2000, 0x1340},
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{0x2020, 0x1340}, {0x2040, 0x1340}, {0x2060, 0x1340}, {0x2080, 0x1340},
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{0x13eb, 0x15bb}, {0x1303, 0x06d6}, {0x1304, 0x0700}, {0x13E2, 0x003F},
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{0x13F9, 0x0090}, {0x121e, 0x03CA}, {0x1233, 0x0352}, {0x1237, 0x00a0},
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{0x123a, 0x0030}, {0x1239, 0x0084}, {0x0301, 0x1000}, {0x1349, 0x001F},
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{0x18e0, 0x4004}, {0x122b, 0x641c}, {0x1305, 0xc000}, {0x1200, 0x7fcb},
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{0x0884, 0x0003}, {0x06eb, 0x0001}, {0x00cf, 0xffff}, {0x00d0, 0x0007},
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{0x00ce, 0x48b0}, {0x00ce, 0x48b0}, {0x0398, 0xffff}, {0x0399, 0x0007},
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{0x0300, 0x0001}, {0x03fa, 0x0007}, {0x08c8, 0x00c0}, {0x0a30, 0x020e},
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{0x0800, 0x0000}, {0x0802, 0x0000}, {0x09da, 0x0017}, {0x1d32, 0x0002},
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};
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static const struct rtl8367b_initval rtl8367s_initvals[] = {
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/* Special init for RTL8367SB in RGMII mode with some comments */
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/* phy port eee init */
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{0x0018, 0x0f00}, {0x1d15, 0x0a69}, {0x2014, 0x0000}, {0x2708, 0x0006},
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{0x0038, 0x0f00}, {0x1d15, 0x0a69}, {0x2034, 0x0000}, {0x2748, 0x0006},
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{0x0058, 0x0f00}, {0x1d15, 0x0a69}, {0x2054, 0x0000}, {0x2748, 0x0006},
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{0x0078, 0x0f00}, {0x1d15, 0x0a69}, {0x2074, 0x0000}, {0x2768, 0x0006},
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{0x0018, 0x0f00}, {0x1d15, 0x0a69}, {0x2094, 0x0000}, {0x2788, 0x0006},
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/* enable phy 0-4 - after reset phy is disabled */
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{0x1d15, 0x0a69}, {0x2000, 0x1340}, {0x2020, 0x1340}, {0x2040, 0x1340},
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{0x2060, 0x1340}, {0x2080, 0x1340},
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/* standard init */
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{0x13eb, 0x15bb}, {0x1303, 0x06d6}, {0x1304, 0x0700}, {0x13E2, 0x003F},
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{0x13F9, 0x0090},
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/* add init extended interface2 mode == rgmii explicitly */
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{0x1303, 0x0767}, {0x1304, 0x7777}, {0x1305, 0xc000}, {0x13E2, 0x01fd},
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{0x13c3, 0x0001}, {0x13c4, 0x1076}, {0x13c5, 0x000a},
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/*end init ext2 mode*/
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{0x121e, 0x03CA}, {0x1233, 0x0352}, {0x1237, 0x00a0}, {0x123a, 0x0030},
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{0x1239, 0x0084}, {0x0301, 0x1000}, {0x1349, 0x001F}, {0x18e0, 0x4004},
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{0x122b, 0x641c}, {0x1305, 0xc000}, {0x1200, 0x7fcb}, {0x0884, 0x0003},
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{0x06eb, 0x0001}, {0x00cf, 0xffff}, {0x00d0, 0x0007}, {0x00ce, 0x48b0},
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{0x0398, 0xffff}, {0x0399, 0x0007}, {0x0300, 0x0001}, {0x03fa, 0x0007},
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{0x08c8, 0x00c0}, {0x0a30, 0x020e}, {0x0800, 0x0000}, {0x0802, 0x0000},
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{0x09da, 0x0017}, {0x1d32, 0x0002}, {0x13c2, 0x0000},
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};
|
||||
static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
|
||||
const struct rtl8367b_initval *initvals,
|
||||
int count)
|
||||
|
|
@ -612,6 +679,10 @@ static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
|
|||
int err;
|
||||
int i;
|
||||
|
||||
if (rtl_device_id == 0x0020) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
REG_WR(smi, initvals[i].reg, initvals[i].val);
|
||||
|
||||
|
|
@ -727,6 +798,11 @@ static int rtl8367b_init_regs(struct rtl8366_smi *smi)
|
|||
rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
|
||||
RTL8367B_CHIP_VER_RLVID_MASK;
|
||||
|
||||
if (of_device_is_compatible(smi->parent->of_node,
|
||||
"realtek,rtl8367s")) {
|
||||
initvals = rtl8367c_initvals0;
|
||||
count = ARRAY_SIZE(rtl8367c_initvals0);
|
||||
} else {
|
||||
switch (rlvid) {
|
||||
case 0:
|
||||
initvals = rtl8367r_vb_initvals_0;
|
||||
|
|
@ -742,6 +818,7 @@ static int rtl8367b_init_regs(struct rtl8366_smi *smi)
|
|||
dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
/* TODO: disable RLTP */
|
||||
|
||||
|
|
@ -779,7 +856,45 @@ static int rtl8367b_reset_chip(struct rtl8366_smi *smi)
|
|||
static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
|
||||
enum rtl8367_extif_mode mode)
|
||||
{
|
||||
int err;
|
||||
int err, i;
|
||||
/* for SGMII, works (from rtl8367s_api.c in TL-R600VPN v4 GPL) */
|
||||
unsigned int redData[][2] = {
|
||||
{0x7180, 0x2},
|
||||
{0x04D7, 0x0480},
|
||||
{0xF994, 0x0481},
|
||||
{0x31A2, 0x0482},
|
||||
{0x6960, 0x0483},
|
||||
{0x9728, 0x0484},
|
||||
{0x9D85, 0x0423},
|
||||
{0xD810, 0x0424},
|
||||
{0x0F80, 0x0001}
|
||||
};
|
||||
|
||||
/*
|
||||
* for HSGMII, works
|
||||
* (from rtl8367c_asicdrv_port.c in TL-R600VPN v4 GPL,
|
||||
* based on redDataHB and customized like redData)
|
||||
*/
|
||||
unsigned int redDataH[][2] = {
|
||||
{0x7180, 0x2},
|
||||
{0x82F0, 0x0500},
|
||||
{0xF195, 0x0501},
|
||||
{0x31A2, 0x0502},
|
||||
{0x7960, 0x0503},
|
||||
{0x9728, 0x0504},
|
||||
{0x9D85, 0x0423},
|
||||
{0xD810, 0x0424},
|
||||
{0x0F80, 0x0001},
|
||||
{0x83F2, 0x002E}
|
||||
};
|
||||
|
||||
if ((mode == RTL8367S_EXTIF_MODE_SGMII ||
|
||||
mode == RTL8367S_EXTIF_MODE_HSGMII)
|
||||
&& id != RTL8367_EXTIF1) {
|
||||
dev_err(smi->parent,
|
||||
"SGMII/HSGMII mode is only available in extif1\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* set port mode */
|
||||
switch (mode) {
|
||||
|
|
@ -787,7 +902,7 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
|
|||
REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
|
||||
RTL8367B_DEBUG0_SEL33(id),
|
||||
RTL8367B_DEBUG0_SEL33(id));
|
||||
if (id <= 1) {
|
||||
if (id <= RTL8367_EXTIF1) {
|
||||
REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
|
||||
RTL8367B_DEBUG0_DRI(id) |
|
||||
RTL8367B_DEBUG0_DRI_RG(id) |
|
||||
|
|
@ -823,6 +938,17 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
|
|||
RTL8367B_DEBUG0_SEL33(id),
|
||||
RTL8367B_DEBUG0_SEL33(id));
|
||||
REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6));
|
||||
|
||||
if (of_device_is_compatible(smi->parent->of_node,
|
||||
"realtek,rtl8367s")) {
|
||||
REG_RMW(smi, RTL8367S_EXT_TXC_DLY_REG,
|
||||
RTL8367S_EXT_GMII_TX_DELAY_MASK
|
||||
<< RTL8367S_EXT1_GMII_TX_DELAY_SHIFT |
|
||||
RTL8367S_EXT_GMII_TX_DELAY_MASK
|
||||
<< RTL8367S_EXT0_GMII_TX_DELAY_SHIFT,
|
||||
5 << RTL8367S_EXT1_GMII_TX_DELAY_SHIFT | /* shoud be configured */
|
||||
6 << RTL8367S_EXT0_GMII_TX_DELAY_SHIFT); /* in set_rgmii_delay? */
|
||||
}
|
||||
break;
|
||||
|
||||
case RTL8367_EXTIF_MODE_MII_MAC:
|
||||
|
|
@ -832,13 +958,49 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
|
|||
REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0);
|
||||
break;
|
||||
|
||||
case RTL8367S_EXTIF_MODE_SGMII:
|
||||
if (!of_device_is_compatible(smi->parent->of_node,
|
||||
"realtek,rtl8367s"))
|
||||
goto invalid_mode;
|
||||
|
||||
/* setup SerDes register for SGMII */
|
||||
for (i = 0; i <= 7; i++) {
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, redData[i][0]);
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, redData[i][1]);
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
|
||||
RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
|
||||
}
|
||||
break;
|
||||
|
||||
case RTL8367S_EXTIF_MODE_HSGMII:
|
||||
if (!of_device_is_compatible(smi->parent->of_node,
|
||||
"realtek,rtl8367s"))
|
||||
goto invalid_mode;
|
||||
|
||||
/* setup SerDes register for HSGMII */
|
||||
for (i = 0; i <= 8; i++) {
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, redDataH[i][0]);
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, redDataH[i][1]);
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
|
||||
RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(smi->parent,
|
||||
"invalid mode for external interface %d\n", id);
|
||||
return -EINVAL;
|
||||
goto invalid_mode;
|
||||
}
|
||||
|
||||
if (id <= 1)
|
||||
if (id == RTL8367_EXTIF1 &&
|
||||
of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s")) {
|
||||
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_MAC8_SEL_HSGMII_MASK,
|
||||
(mode == RTL8367S_EXTIF_MODE_HSGMII)
|
||||
? RTL8367S_CFG_MAC8_SEL_HSGMII_MASK : 0);
|
||||
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_MAC8_SEL_SGMII,
|
||||
(mode == RTL8367S_EXTIF_MODE_SGMII)
|
||||
? RTL8367S_CFG_MAC8_SEL_SGMII : 0);
|
||||
}
|
||||
|
||||
if (id <= RTL8367_EXTIF1)
|
||||
REG_RMW(smi, RTL8367B_DIS_REG,
|
||||
RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
|
||||
mode << RTL8367B_DIS_RGMII_SHIFT(id));
|
||||
|
|
@ -847,7 +1009,20 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
|
|||
RTL8367B_DIS2_RGMII_MASK << RTL8367B_DIS2_RGMII_SHIFT,
|
||||
mode << RTL8367B_DIS2_RGMII_SHIFT);
|
||||
|
||||
if (mode == RTL8367S_EXTIF_MODE_SGMII ||
|
||||
mode == RTL8367S_EXTIF_MODE_HSGMII) {
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, 0x7106);
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, 0x0003);
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
|
||||
RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
invalid_mode:
|
||||
dev_err(smi->parent,
|
||||
"invalid mode for external interface %d\n", id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
|
||||
|
|
@ -857,6 +1032,20 @@ static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
|
|||
u32 val;
|
||||
int err;
|
||||
|
||||
if (id == RTL8367_EXTIF1 &&
|
||||
of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s")) {
|
||||
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_FDUP,
|
||||
pa->duplex ? RTL8367S_CFG_SGMII_FDUP : 0);
|
||||
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_SPD_MASK,
|
||||
pa->speed << RTL8367S_CFG_SGMII_SPD_SHIFT);
|
||||
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_LINK,
|
||||
pa->link ? RTL8367S_CFG_SGMII_LINK : 0);
|
||||
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_TXFC,
|
||||
pa->txpause ? RTL8367S_CFG_SGMII_TXFC : 0);
|
||||
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_RXFC,
|
||||
pa->rxpause ? RTL8367S_CFG_SGMII_RXFC : 0);
|
||||
}
|
||||
|
||||
mask = (RTL8367B_DI_FORCE_MODE |
|
||||
RTL8367B_DI_FORCE_NWAY |
|
||||
RTL8367B_DI_FORCE_TXPAUSE |
|
||||
|
|
@ -918,6 +1107,15 @@ static int rtl8367b_extif_init(struct rtl8366_smi *smi, int id,
|
|||
cfg->rxdelay);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (of_device_is_compatible(smi->parent->of_node,
|
||||
"realtek,rtl8367s")) {
|
||||
/* disable pre-emphasis */
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, 0x28A0);
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, 0x0482);
|
||||
REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
|
||||
RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -928,6 +1126,7 @@ static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
|
|||
const char *name)
|
||||
{
|
||||
struct rtl8367_extif_config *cfg;
|
||||
enum rtl8367_port_speed speed;
|
||||
const __be32 *prop;
|
||||
int size;
|
||||
int err;
|
||||
|
|
@ -953,7 +1152,11 @@ static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
|
|||
cfg->ability.rxpause = be32_to_cpup(prop++);
|
||||
cfg->ability.link = be32_to_cpup(prop++);
|
||||
cfg->ability.duplex = be32_to_cpup(prop++);
|
||||
cfg->ability.speed = be32_to_cpup(prop++);
|
||||
speed = be32_to_cpup(prop++);
|
||||
if (of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s") &&
|
||||
cfg->mode == RTL8367S_EXTIF_MODE_HSGMII)
|
||||
speed = RTL8367_PORT_SPEED_1000;
|
||||
cfg->ability.speed = speed;
|
||||
|
||||
err = rtl8367b_extif_init(smi, id, cfg);
|
||||
kfree(cfg);
|
||||
|
|
@ -982,23 +1185,28 @@ static int rtl8367b_setup(struct rtl8366_smi *smi)
|
|||
|
||||
/* initialize external interfaces */
|
||||
if (smi->parent->of_node) {
|
||||
err = rtl8367b_extif_init_of(smi, 0, "realtek,extif0");
|
||||
err = rtl8367b_extif_init_of(smi, RTL8367_EXTIF0,
|
||||
"realtek,extif0");
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1");
|
||||
err = rtl8367b_extif_init_of(smi, RTL8367_EXTIF1,
|
||||
"realtek,extif1");
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = rtl8367b_extif_init_of(smi, 2, "realtek,extif2");
|
||||
err = rtl8367b_extif_init_of(smi, RTL8367_EXTIF2,
|
||||
"realtek,extif2");
|
||||
if (err)
|
||||
return err;
|
||||
} else {
|
||||
err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
|
||||
err = rtl8367b_extif_init(smi, RTL8367_EXTIF0,
|
||||
pdata->extif0_cfg);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg);
|
||||
err = rtl8367b_extif_init(smi, RTL8367_EXTIF1,
|
||||
pdata->extif1_cfg);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
|
@ -1273,12 +1481,16 @@ static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
|
|||
struct switch_port_link *link)
|
||||
{
|
||||
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
||||
u32 data = 0;
|
||||
u32 data = 0, sds_misc = 0;
|
||||
u32 speed;
|
||||
|
||||
if (port >= RTL8367B_NUM_PORTS)
|
||||
return -EINVAL;
|
||||
|
||||
if (port == 6 &&
|
||||
of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s"))
|
||||
rtl8366_smi_read_reg(smi, RTL8367S_SDS_MISC, &sds_misc);
|
||||
|
||||
rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
|
||||
|
||||
link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
|
||||
|
|
@ -1299,7 +1511,10 @@ static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
|
|||
link->speed = SWITCH_PORT_SPEED_100;
|
||||
break;
|
||||
case 2:
|
||||
link->speed = SWITCH_PORT_SPEED_1000;
|
||||
link->speed = (((sds_misc & RTL8367S_CFG_MAC8_SEL_HSGMII_MASK)
|
||||
>> RTL8367S_CFG_MAC8_SEL_HSGMII_SHIFT) == 1)
|
||||
? SWITCH_PORT_SPEED_2500
|
||||
: SWITCH_PORT_SPEED_1000;
|
||||
break;
|
||||
default:
|
||||
link->speed = SWITCH_PORT_SPEED_UNKNOWN;
|
||||
|
|
@ -1543,6 +1758,18 @@ static int rtl8367b_detect(struct rtl8366_smi *smi)
|
|||
return ret;
|
||||
}
|
||||
|
||||
dev_info(smi->parent,
|
||||
"found chip num:%04x ver:%04x, mode:%04x\n",
|
||||
chip_num, chip_ver, chip_mode);
|
||||
|
||||
/* rtl8367s: known chip num:6367 ver:00a0, mode:00a0 */
|
||||
|
||||
if (of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s")) {
|
||||
if (chip_ver == 0x00a0)
|
||||
chip_name = "8367S";
|
||||
else
|
||||
goto unknown_chip;
|
||||
} else {
|
||||
switch (chip_ver) {
|
||||
case 0x0020:
|
||||
case 0x1000:
|
||||
|
|
@ -1552,15 +1779,19 @@ static int rtl8367b_detect(struct rtl8366_smi *smi)
|
|||
chip_name = "8367R-VB";
|
||||
break;
|
||||
default:
|
||||
dev_err(smi->parent,
|
||||
"unknown chip num:%04x ver:%04x, mode:%04x\n",
|
||||
chip_num, chip_ver, chip_mode);
|
||||
return -ENODEV;
|
||||
goto unknown_chip;
|
||||
}
|
||||
}
|
||||
|
||||
dev_info(smi->parent, "RTL%s chip found\n", chip_name);
|
||||
|
||||
return 0;
|
||||
|
||||
unknown_chip:
|
||||
dev_err(smi->parent,
|
||||
"unknown chip num:%04x ver:%04x, mode:%04x\n",
|
||||
chip_num, chip_ver, chip_mode);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static struct rtl8366_smi_ops rtl8367b_smi_ops = {
|
||||
|
|
@ -1599,11 +1830,17 @@ static int rtl8367b_probe(struct platform_device *pdev)
|
|||
smi->ops = &rtl8367b_smi_ops;
|
||||
smi->num_ports = RTL8367B_NUM_PORTS;
|
||||
if (of_property_read_u32(pdev->dev.of_node, "cpu_port", &smi->cpu_port)
|
||||
|| smi->cpu_port >= smi->num_ports)
|
||||
|| smi->cpu_port >= smi->num_ports) {
|
||||
if (of_device_is_compatible(pdev->dev.of_node, "realtek,rtl8367s"))
|
||||
smi->cpu_port = RTL8367S_CPU_PORT_NUM;
|
||||
else
|
||||
smi->cpu_port = RTL8367B_CPU_PORT_NUM;
|
||||
}
|
||||
smi->num_vlan_mc = RTL8367B_NUM_VLANS;
|
||||
smi->mib_counters = rtl8367b_mib_counters;
|
||||
smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);
|
||||
if (of_device_is_compatible(pdev->dev.of_node, "realtek,rtl8367s"))
|
||||
smi->phy_id = RTL8367S_PHY_ADDR;
|
||||
|
||||
err = rtl8366_smi_init(smi);
|
||||
if (err)
|
||||
|
|
@ -1650,6 +1887,7 @@ static void rtl8367b_shutdown(struct platform_device *pdev)
|
|||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id rtl8367b_match[] = {
|
||||
{ .compatible = "realtek,rtl8367b" },
|
||||
{ .compatible = "realtek,rtl8367s" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rtl8367b_match);
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@ enum rtl8367_port_speed {
|
|||
RTL8367_PORT_SPEED_10 = 0,
|
||||
RTL8367_PORT_SPEED_100,
|
||||
RTL8367_PORT_SPEED_1000,
|
||||
RTL8367S_PORT_SPEED_500M,
|
||||
RTL8367S_PORT_SPEED_2500M,
|
||||
};
|
||||
|
||||
struct rtl8367_port_ability {
|
||||
|
|
@ -30,6 +32,12 @@ struct rtl8367_port_ability {
|
|||
enum rtl8367_port_speed speed;
|
||||
};
|
||||
|
||||
enum rtl8367_extif {
|
||||
RTL8367_EXTIF0 = 0,
|
||||
RTL8367_EXTIF1,
|
||||
RTL8367_EXTIF2,
|
||||
};
|
||||
|
||||
enum rtl8367_extif_mode {
|
||||
RTL8367_EXTIF_MODE_DISABLED = 0,
|
||||
RTL8367_EXTIF_MODE_RGMII,
|
||||
|
|
@ -39,9 +47,11 @@ enum rtl8367_extif_mode {
|
|||
RTL8367_EXTIF_MODE_TMII_PHY,
|
||||
RTL8367_EXTIF_MODE_GMII,
|
||||
RTL8367_EXTIF_MODE_RGMII_33V,
|
||||
RTL8367B_EXTIF_MODE_RMII_MAC = 7,
|
||||
RTL8367B_EXTIF_MODE_RMII_MAC,
|
||||
RTL8367B_EXTIF_MODE_RMII_PHY,
|
||||
RTL8367B_EXTIF_MODE_RGMII_33V,
|
||||
RTL8367S_EXTIF_MODE_SGMII,
|
||||
RTL8367S_EXTIF_MODE_HSGMII,
|
||||
};
|
||||
|
||||
struct rtl8367_extif_config {
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@ enum switch_port_speed {
|
|||
SWITCH_PORT_SPEED_10 = 10,
|
||||
SWITCH_PORT_SPEED_100 = 100,
|
||||
SWITCH_PORT_SPEED_1000 = 1000,
|
||||
SWITCH_PORT_SPEED_2500 = 2500,
|
||||
};
|
||||
|
||||
struct switch_port_link {
|
||||
|
|
|
|||
|
|
@ -39,6 +39,10 @@ rockchip_setup_interfaces()
|
|||
friendlyarm,nanopi-r5s)
|
||||
ucidef_set_interfaces_lan_wan "eth1 eth2" "eth0"
|
||||
;;
|
||||
aio,aio-3399b)
|
||||
ucidef_add_switch "switch0" \
|
||||
"7@eth0" "0:lan:0" "1:lan:1" "2:lan:2" "3:lan:3" "4:lan:4" "5:lan:5" "6:wan:6"
|
||||
;;
|
||||
*)
|
||||
ucidef_set_interface_lan 'eth0'
|
||||
;;
|
||||
|
|
@ -97,6 +101,13 @@ rockchip_setup_macs()
|
|||
wan_mac=$(nanopi_r4s_get_mac wan)
|
||||
lan_mac=$(nanopi_r4s_get_mac lan)
|
||||
;;
|
||||
aio,aio-3399b)
|
||||
[ -d /sys/class/block/mmcblk0/mmcblk0boot0 ]&&mmcnb=mmcblk0
|
||||
[ -d /sys/class/block/mmcblk1/mmcblk1boot0 ]&&mmcnb=mmcblk1
|
||||
[ -d /sys/class/block/mmcblk2/mmcblk2boot0 ]&&mmcnb=mmcblk2
|
||||
wan_mac=$(macaddr_generate_from_mmc_cid $mmcnb)
|
||||
lan_mac=$(macaddr_add "$wan_mac" +1)
|
||||
;;
|
||||
friendlyarm,nanopi-r5c|\
|
||||
friendlyarm,nanopi-r5s|\
|
||||
sharevdi,guangmiao-g4c)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
#!/bin/sh
|
||||
board=$(cat /tmp/sysinfo/board_name)
|
||||
case "$board" in
|
||||
aio,aio-3399b)
|
||||
uci -q set network.lan.ipaddr="192.168.9.1"
|
||||
uci -q set network.pon=interface
|
||||
uci -q set network.pon.proto="static"
|
||||
uci -q set network.pon.ifname="eth0.2"
|
||||
uci -q set network.pon.delegate="0"
|
||||
uci -q set network.pon.ipaddr="192.168.1.254"
|
||||
uci -q set network.pon.netmask="255.255.255.0"
|
||||
uci -q set network.pon.metric="100"
|
||||
uci -q set network.pon_route=route
|
||||
uci -q set network.pon_route.interface='pon'
|
||||
uci -q set network.pon_route.target='192.168.1.10'
|
||||
uci -q set network.pon_route.netmask='255.255.255.0'
|
||||
uci -q set network.pon_route.gateway='192.168.1.254'
|
||||
uci -q set network.pon_route.metric='100'
|
||||
uci -q commit network
|
||||
;;
|
||||
*)
|
||||
exit 0
|
||||
;;
|
||||
esac
|
||||
exit 0
|
||||
|
|
@ -550,6 +550,7 @@ CONFIG_SCSI_SAS_LIBSAS=y
|
|||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
# CONFIG_SENSORS_ARM_SCMI is not set
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
CONFIG_SENSORS_PWM_FAN=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -52,6 +52,16 @@ define Device/ezpro_mrkaio-m68s-plus
|
|||
endef
|
||||
TARGET_DEVICES += ezpro_mrkaio-m68s-plus
|
||||
|
||||
define Device/aio-3399b
|
||||
DEVICE_VENDOR := AllInOne
|
||||
DEVICE_MODEL := AIO-3399B
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := aio-3399b-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-brcmfmac brcmfmac-nvram-4356-sdio cypress-firmware-4356-sdio swconfig kmod-ata-ahci kmod-nvme aio-3399b-firmware kmod-switch-rtl8367b wpad-openssl
|
||||
endef
|
||||
TARGET_DEVICES += aio-3399b
|
||||
|
||||
define Device/fastrhino_common
|
||||
DEVICE_VENDOR := FastRhino
|
||||
SOC := rk3568
|
||||
|
|
|
|||
|
|
@ -0,0 +1,10 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-aio-3399b.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-king3399.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
|
|
@ -4,6 +4,7 @@
|
|||
# This is free software, licensed under the GNU General Public License v2.
|
||||
# See /LICENSE for more information.
|
||||
#
|
||||
export FORCE_UNSAFE_CONFIGURE=1
|
||||
include $(TOPDIR)/rules.mk
|
||||
|
||||
PKG_NAME:=tar
|
||||
|
|
|
|||
Loading…
Reference in New Issue