Revert "rockchip: rk3568 overclock to 2.2GHz"
This reverts commit c28b7a5625.
This commit is contained in:
AmadeusGhost
parent
36a2481b9a
commit
61b7a5aa75
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@ -1,311 +0,0 @@
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/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/rockchip-ddr.h>
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#include <dt-bindings/memory/rk3328-dram.h>
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/ {
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ddr_timing: ddr_timing {
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compatible = "rockchip,ddr-timing";
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ddr3_speed_bin = <DDR3_DEFAULT>;
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ddr4_speed_bin = <DDR4_DEFAULT>;
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pd_idle = <0>;
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sr_idle = <0>;
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sr_mc_gate_idle = <0>;
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srpd_lite_idle = <0>;
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standby_idle = <0>;
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auto_pd_dis_freq = <1066>;
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auto_sr_dis_freq = <800>;
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ddr3_dll_dis_freq = <300>;
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ddr4_dll_dis_freq = <625>;
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phy_dll_dis_freq = <400>;
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ddr3_odt_dis_freq = <100>;
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phy_ddr3_odt_dis_freq = <100>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
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phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
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phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
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phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
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lpddr3_odt_dis_freq = <666>;
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phy_lpddr3_odt_dis_freq = <666>;
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lpddr3_drv = <LP3_DS_40ohm>;
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lpddr3_odt = <LP3_ODT_240ohm>;
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phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
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phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
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lpddr4_odt_dis_freq = <800>;
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phy_lpddr4_odt_dis_freq = <800>;
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lpddr4_drv = <LP4_PDDS_60ohm>;
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lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
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phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
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phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
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phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
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phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
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ddr4_odt_dis_freq = <666>;
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phy_ddr4_odt_dis_freq = <666>;
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ddr4_drv = <DDR4_DS_34ohm>;
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ddr4_odt = <DDR4_RTT_NOM_240ohm>;
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phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
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phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
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/* CA de-skew, one step is 47.8ps, range 0-15 */
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ddr3a1_ddr4a9_de-skew = <7>;
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ddr3a0_ddr4a10_de-skew = <7>;
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ddr3a3_ddr4a6_de-skew = <8>;
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ddr3a2_ddr4a4_de-skew = <8>;
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ddr3a5_ddr4a8_de-skew = <7>;
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ddr3a4_ddr4a5_de-skew = <9>;
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ddr3a7_ddr4a11_de-skew = <7>;
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ddr3a6_ddr4a7_de-skew = <9>;
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ddr3a9_ddr4a0_de-skew = <8>;
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ddr3a8_ddr4a13_de-skew = <7>;
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ddr3a11_ddr4a3_de-skew = <9>;
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ddr3a10_ddr4cs0_de-skew = <7>;
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ddr3a13_ddr4a2_de-skew = <8>;
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ddr3a12_ddr4ba1_de-skew = <7>;
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ddr3a15_ddr4odt0_de-skew = <7>;
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ddr3a14_ddr4a1_de-skew = <8>;
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ddr3ba1_ddr4a15_de-skew = <7>;
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ddr3ba0_ddr4bg0_de-skew = <7>;
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ddr3ras_ddr4cke_de-skew = <7>;
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ddr3ba2_ddr4ba0_de-skew = <8>;
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ddr3we_ddr4bg1_de-skew = <8>;
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ddr3cas_ddr4a12_de-skew = <7>;
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ddr3ckn_ddr4ckn_de-skew = <8>;
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ddr3ckp_ddr4ckp_de-skew = <8>;
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ddr3cke_ddr4a16_de-skew = <8>;
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ddr3odt0_ddr4a14_de-skew = <7>;
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ddr3cs0_ddr4act_de-skew = <8>;
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ddr3reset_ddr4reset_de-skew = <7>;
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ddr3cs1_ddr4cs1_de-skew = <7>;
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ddr3odt1_ddr4odt1_de-skew = <7>;
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/* DATA de-skew
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* RX one step is 25.1ps, range 0-15
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* TX one step is 47.8ps, range 0-15
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*/
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cs0_dm0_rx_de-skew = <7>;
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cs0_dm0_tx_de-skew = <8>;
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cs0_dq0_rx_de-skew = <7>;
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cs0_dq0_tx_de-skew = <8>;
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cs0_dq1_rx_de-skew = <7>;
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cs0_dq1_tx_de-skew = <8>;
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cs0_dq2_rx_de-skew = <7>;
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cs0_dq2_tx_de-skew = <8>;
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cs0_dq3_rx_de-skew = <7>;
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cs0_dq3_tx_de-skew = <8>;
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cs0_dq4_rx_de-skew = <7>;
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cs0_dq4_tx_de-skew = <8>;
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cs0_dq5_rx_de-skew = <7>;
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cs0_dq5_tx_de-skew = <8>;
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cs0_dq6_rx_de-skew = <7>;
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cs0_dq6_tx_de-skew = <8>;
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cs0_dq7_rx_de-skew = <7>;
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cs0_dq7_tx_de-skew = <8>;
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cs0_dqs0_rx_de-skew = <6>;
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cs0_dqs0p_tx_de-skew = <9>;
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cs0_dqs0n_tx_de-skew = <9>;
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cs0_dm1_rx_de-skew = <7>;
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cs0_dm1_tx_de-skew = <7>;
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cs0_dq8_rx_de-skew = <7>;
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cs0_dq8_tx_de-skew = <8>;
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cs0_dq9_rx_de-skew = <7>;
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cs0_dq9_tx_de-skew = <7>;
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cs0_dq10_rx_de-skew = <7>;
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cs0_dq10_tx_de-skew = <8>;
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cs0_dq11_rx_de-skew = <7>;
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cs0_dq11_tx_de-skew = <7>;
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cs0_dq12_rx_de-skew = <7>;
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cs0_dq12_tx_de-skew = <8>;
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cs0_dq13_rx_de-skew = <7>;
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cs0_dq13_tx_de-skew = <7>;
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cs0_dq14_rx_de-skew = <7>;
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cs0_dq14_tx_de-skew = <8>;
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cs0_dq15_rx_de-skew = <7>;
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cs0_dq15_tx_de-skew = <7>;
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cs0_dqs1_rx_de-skew = <7>;
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cs0_dqs1p_tx_de-skew = <9>;
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cs0_dqs1n_tx_de-skew = <9>;
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cs0_dm2_rx_de-skew = <7>;
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cs0_dm2_tx_de-skew = <8>;
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cs0_dq16_rx_de-skew = <7>;
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cs0_dq16_tx_de-skew = <8>;
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cs0_dq17_rx_de-skew = <7>;
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cs0_dq17_tx_de-skew = <8>;
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cs0_dq18_rx_de-skew = <7>;
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cs0_dq18_tx_de-skew = <8>;
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cs0_dq19_rx_de-skew = <7>;
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cs0_dq19_tx_de-skew = <8>;
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cs0_dq20_rx_de-skew = <7>;
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cs0_dq20_tx_de-skew = <8>;
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cs0_dq21_rx_de-skew = <7>;
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cs0_dq21_tx_de-skew = <8>;
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cs0_dq22_rx_de-skew = <7>;
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cs0_dq22_tx_de-skew = <8>;
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cs0_dq23_rx_de-skew = <7>;
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cs0_dq23_tx_de-skew = <8>;
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cs0_dqs2_rx_de-skew = <6>;
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cs0_dqs2p_tx_de-skew = <9>;
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cs0_dqs2n_tx_de-skew = <9>;
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cs0_dm3_rx_de-skew = <7>;
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cs0_dm3_tx_de-skew = <7>;
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cs0_dq24_rx_de-skew = <7>;
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cs0_dq24_tx_de-skew = <8>;
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cs0_dq25_rx_de-skew = <7>;
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cs0_dq25_tx_de-skew = <7>;
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cs0_dq26_rx_de-skew = <7>;
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cs0_dq26_tx_de-skew = <7>;
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cs0_dq27_rx_de-skew = <7>;
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cs0_dq27_tx_de-skew = <7>;
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cs0_dq28_rx_de-skew = <7>;
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cs0_dq28_tx_de-skew = <7>;
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cs0_dq29_rx_de-skew = <7>;
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cs0_dq29_tx_de-skew = <7>;
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cs0_dq30_rx_de-skew = <7>;
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cs0_dq30_tx_de-skew = <7>;
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cs0_dq31_rx_de-skew = <7>;
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cs0_dq31_tx_de-skew = <7>;
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cs0_dqs3_rx_de-skew = <7>;
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cs0_dqs3p_tx_de-skew = <9>;
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cs0_dqs3n_tx_de-skew = <9>;
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cs1_dm0_rx_de-skew = <7>;
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cs1_dm0_tx_de-skew = <8>;
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cs1_dq0_rx_de-skew = <7>;
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cs1_dq0_tx_de-skew = <8>;
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cs1_dq1_rx_de-skew = <7>;
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cs1_dq1_tx_de-skew = <8>;
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cs1_dq2_rx_de-skew = <7>;
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cs1_dq2_tx_de-skew = <8>;
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cs1_dq3_rx_de-skew = <7>;
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cs1_dq3_tx_de-skew = <8>;
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cs1_dq4_rx_de-skew = <7>;
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cs1_dq4_tx_de-skew = <8>;
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cs1_dq5_rx_de-skew = <7>;
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cs1_dq5_tx_de-skew = <8>;
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cs1_dq6_rx_de-skew = <7>;
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cs1_dq6_tx_de-skew = <8>;
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cs1_dq7_rx_de-skew = <7>;
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cs1_dq7_tx_de-skew = <8>;
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cs1_dqs0_rx_de-skew = <6>;
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cs1_dqs0p_tx_de-skew = <9>;
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cs1_dqs0n_tx_de-skew = <9>;
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cs1_dm1_rx_de-skew = <7>;
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cs1_dm1_tx_de-skew = <7>;
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cs1_dq8_rx_de-skew = <7>;
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cs1_dq8_tx_de-skew = <8>;
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cs1_dq9_rx_de-skew = <7>;
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cs1_dq9_tx_de-skew = <7>;
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cs1_dq10_rx_de-skew = <7>;
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cs1_dq10_tx_de-skew = <8>;
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cs1_dq11_rx_de-skew = <7>;
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cs1_dq11_tx_de-skew = <7>;
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cs1_dq12_rx_de-skew = <7>;
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cs1_dq12_tx_de-skew = <8>;
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cs1_dq13_rx_de-skew = <7>;
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cs1_dq13_tx_de-skew = <7>;
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cs1_dq14_rx_de-skew = <7>;
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cs1_dq14_tx_de-skew = <8>;
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cs1_dq15_rx_de-skew = <7>;
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cs1_dq15_tx_de-skew = <7>;
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cs1_dqs1_rx_de-skew = <7>;
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cs1_dqs1p_tx_de-skew = <9>;
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cs1_dqs1n_tx_de-skew = <9>;
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cs1_dm2_rx_de-skew = <7>;
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cs1_dm2_tx_de-skew = <8>;
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cs1_dq16_rx_de-skew = <7>;
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cs1_dq16_tx_de-skew = <8>;
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cs1_dq17_rx_de-skew = <7>;
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cs1_dq17_tx_de-skew = <8>;
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cs1_dq18_rx_de-skew = <7>;
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cs1_dq18_tx_de-skew = <8>;
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cs1_dq19_rx_de-skew = <7>;
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cs1_dq19_tx_de-skew = <8>;
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cs1_dq20_rx_de-skew = <7>;
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cs1_dq20_tx_de-skew = <8>;
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cs1_dq21_rx_de-skew = <7>;
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cs1_dq21_tx_de-skew = <8>;
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cs1_dq22_rx_de-skew = <7>;
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cs1_dq22_tx_de-skew = <8>;
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cs1_dq23_rx_de-skew = <7>;
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cs1_dq23_tx_de-skew = <8>;
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cs1_dqs2_rx_de-skew = <6>;
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cs1_dqs2p_tx_de-skew = <9>;
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cs1_dqs2n_tx_de-skew = <9>;
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cs1_dm3_rx_de-skew = <7>;
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cs1_dm3_tx_de-skew = <7>;
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cs1_dq24_rx_de-skew = <7>;
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cs1_dq24_tx_de-skew = <8>;
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cs1_dq25_rx_de-skew = <7>;
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cs1_dq25_tx_de-skew = <7>;
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cs1_dq26_rx_de-skew = <7>;
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cs1_dq26_tx_de-skew = <7>;
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cs1_dq27_rx_de-skew = <7>;
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cs1_dq27_tx_de-skew = <7>;
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cs1_dq28_rx_de-skew = <7>;
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cs1_dq28_tx_de-skew = <7>;
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cs1_dq29_rx_de-skew = <7>;
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cs1_dq29_tx_de-skew = <7>;
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cs1_dq30_rx_de-skew = <7>;
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cs1_dq30_tx_de-skew = <7>;
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cs1_dq31_rx_de-skew = <7>;
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cs1_dq31_tx_de-skew = <7>;
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cs1_dqs3_rx_de-skew = <7>;
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cs1_dqs3p_tx_de-skew = <9>;
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cs1_dqs3n_tx_de-skew = <9>;
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};
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};
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@ -5,7 +5,6 @@
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/soc/rockchip,vop2.h>
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#include "rk3568.dtsi"
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#include "rk3568-pro-opp.dtsi"
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/ {
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aliases {
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@ -4,7 +4,6 @@
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/dts-v1/;
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#include "rk3568-hinlink-opc.dtsi"
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#include "rk3568-pro-opp.dtsi"
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||||
|
||||
/ {
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model = "HINLINK OPC-H66K Board";
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|
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@ -4,7 +4,6 @@
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/dts-v1/;
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#include "rk3568-hinlink-opc.dtsi"
|
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#include "rk3568-pro-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HINLINK OPC-H68K Board";
|
||||
|
|
|
|||
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@ -1,18 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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||||
|
||||
&cpu0_opp_table {
|
||||
opp-2088000000 {
|
||||
opp-hz = /bits/ 64 <2088000000>;
|
||||
opp-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
opp-2184000000 {
|
||||
opp-hz = /bits/ 64 <2184000000>;
|
||||
opp-microvolt = <1250000>;
|
||||
};
|
||||
|
||||
opp-2208000000 {
|
||||
opp-hz = /bits/ 64 <2208000000>;
|
||||
opp-microvolt = <1275000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -3,7 +3,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "rk3568-fastrhino.dtsi"
|
||||
#include "rk3568-pro-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FastRhino R66S";
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "rk3568-fastrhino.dtsi"
|
||||
#include "rk3568-pro-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FastRhino R68S";
|
||||
|
|
|
|||
|
|
@ -1,66 +0,0 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -53,7 +53,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x0>;
|
||||
- clocks = <&scmi_clk 0>;
|
||||
+ clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
@@ -63,6 +63,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x100>;
|
||||
+ clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
@@ -72,6 +73,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x200>;
|
||||
+ clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
@@ -81,6 +83,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x300>;
|
||||
+ clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
@@ -136,6 +139,7 @@
|
||||
shmem = <&scmi_shmem>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
+ status = "disabled";
|
||||
|
||||
scmi_clk: protocol@14 {
|
||||
reg = <0x14>;
|
||||
@@ -193,6 +197,7 @@
|
||||
scmi_shmem: sram@0 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x0 0x100>;
|
||||
+ status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-rk3568.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3568.c
|
||||
@@ -150,6 +150,12 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
|
||||
}
|
||||
|
||||
static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
|
||||
+ RK3568_CPUCLK_RATE(2208000000, 0, 1, 11, 11, 11, 11),
|
||||
+ RK3568_CPUCLK_RATE(2184000000, 0, 1, 11, 11, 11, 11),
|
||||
+ RK3568_CPUCLK_RATE(2088000000, 0, 1, 9, 9, 9, 9),
|
||||
+ RK3568_CPUCLK_RATE(2016000000, 0, 1, 9, 9, 9, 9),
|
||||
+ RK3568_CPUCLK_RATE(1992000000, 0, 1, 9, 9, 9, 9),
|
||||
+ RK3568_CPUCLK_RATE(1896000000, 0, 1, 7, 7, 7, 7),
|
||||
RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
|
||||
RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
|
||||
RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -53,7 +53,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x0>;
|
||||
- clocks = <&scmi_clk 0>;
|
||||
+ clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
@@ -63,6 +63,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x100>;
|
||||
+ clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
@@ -72,6 +73,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x200>;
|
||||
+ clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
@@ -81,6 +83,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x300>;
|
||||
+ clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
@@ -141,6 +144,7 @@
|
||||
shmem = <&scmi_shmem>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
+ status = "disabled";
|
||||
|
||||
scmi_clk: protocol@14 {
|
||||
reg = <0x14>;
|
||||
@@ -248,6 +252,7 @@
|
||||
scmi_shmem: sram@0 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x0 0x100>;
|
||||
+ status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-rk3568.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3568.c
|
||||
@@ -156,6 +156,12 @@ static struct rockchip_pll_rate_table rk
|
||||
}
|
||||
|
||||
static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
|
||||
+ RK3568_CPUCLK_RATE(2208000000, 0, 1, 11, 11, 11, 11),
|
||||
+ RK3568_CPUCLK_RATE(2184000000, 0, 1, 11, 11, 11, 11),
|
||||
+ RK3568_CPUCLK_RATE(2088000000, 0, 1, 9, 9, 9, 9),
|
||||
+ RK3568_CPUCLK_RATE(2016000000, 0, 1, 9, 9, 9, 9),
|
||||
+ RK3568_CPUCLK_RATE(1992000000, 0, 1, 9, 9, 9, 9),
|
||||
+ RK3568_CPUCLK_RATE(1896000000, 0, 1, 7, 7, 7, 7),
|
||||
RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
|
||||
RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
|
||||
RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),
|
||||
Loading…
Reference in New Issue