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add support for sv901-eaiov1.0,rtl8367s ok

This commit is contained in:
icevel 2023-04-21 15:28:05 +00:00
parent 3713f8b5b1
commit a6bc91008d
12 changed files with 2448 additions and 25 deletions
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14
package/boot/uboot-rockchip/Makefile
View File

@ -146,6 +146,17 @@ define U-Boot/rocktech-mpc1903-rk3399
USE_RKBIN:=1
endef
define U-Boot/scensmart-sv901-rk3399
BUILD_SUBTARGET:=armv8
NAME:=ScenSmart SV901
BUILD_DEVICES:= \
scensmart_sv901
DEPENDS:=+PACKAGE_u-boot-scensmart-sv901-rk3399:arm-trusted-firmware-rk3399
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk3399_bl31_v1.35.elf
USE_RKBIN:=1
endef
define U-Boot/sharevdi-h3399pc-rk3399
BUILD_SUBTARGET:=armv8
NAME:=SHAREVDI H3399PC
@ -272,7 +283,8 @@ UBOOT_TARGETS := \
nanopi-r2c-rk3328 \
nanopi-r2s-rk3328 \
orangepi-r1-plus-rk3328 \
orangepi-r1-plus-lts-rk3328
orangepi-r1-plus-lts-rk3328 \
scensmart-sv901-rk3399
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes

1054
package/boot/uboot-rockchip/patches/309-rockchip-rk3399-Add-support-for-ScenSmart-SV901.patch Executable file
View File

File diff suppressed because it is too large Load Diff

4
target/linux/generic/files/drivers/net/phy/rtl8366_smi.c
View File

@ -256,7 +256,7 @@ static int __rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
int __rtl8366_mdio_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
{
u32 phy_id = MDC_REALTEK_PHY_ADDR;
u32 phy_id = smi->phy_id ? smi->phy_id : MDC_REALTEK_PHY_ADDR;
struct mii_bus *mbus = smi->ext_mbus;
BUG_ON(in_interrupt());
@ -293,7 +293,7 @@ int __rtl8366_mdio_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
static int __rtl8366_mdio_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
{
u32 phy_id = MDC_REALTEK_PHY_ADDR;
u32 phy_id = smi->phy_id ? smi->phy_id : MDC_REALTEK_PHY_ADDR;
struct mii_bus *mbus = smi->ext_mbus;
BUG_ON(in_interrupt());

1
target/linux/generic/files/drivers/net/phy/rtl8366_smi.h
View File

@ -64,6 +64,7 @@ struct rtl8366_smi {
u8 dbg_vlan_4k_page;
#endif
struct mii_bus *ext_mbus;
u32 phy_id;
};
struct rtl8366_vlan_mc {

280
target/linux/generic/files/drivers/net/phy/rtl8367b.c
View File

@ -213,6 +213,23 @@
#define RTL8367B_RTL_MAGIC_ID_REG 0x13c2
#define RTL8367B_RTL_MAGIC_ID_VAL 0x0249
#define RTL8367S_EXT_TXC_DLY_REG 0x13f9
#define RTL8367S_EXT1_GMII_TX_DELAY_SHIFT 12
#define RTL8367S_EXT0_GMII_TX_DELAY_SHIFT 9
#define RTL8367S_EXT_GMII_TX_DELAY_MASK GENMASK(2,0)
#define RTL8367S_SDS_MISC 0x1d11
#define RTL8367S_CFG_SGMII_RXFC BIT(14)
#define RTL8367S_CFG_SGMII_TXFC BIT(13)
#define RTL8367S_CFG_MAC8_SEL_HSGMII_SHIFT 11
#define RTL8367S_CFG_MAC8_SEL_HSGMII_MASK BIT(11)
#define RTL8367S_CFG_SGMII_FDUP BIT(10)
#define RTL8367S_CFG_SGMII_LINK BIT(9)
#define RTL8367S_CFG_SGMII_SPD_SHIFT 7
#define RTL8367S_CFG_SGMII_SPD_MASK GENMASK(8,7)
#define RTL8367S_CFG_MAC8_SEL_SGMII BIT(6)
#define RTL8367B_IA_CTRL_REG 0x1f00
#define RTL8367B_IA_CTRL_RW(_x) ((_x) << 1)
#define RTL8367B_IA_CTRL_RW_READ RTL8367B_IA_CTRL_RW(0)
@ -230,9 +247,18 @@
#define RTL8367B_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r))
/* SerDes indirect access */
#define RTL8367S_SDS_INDACS_CMD_REG 0x6600
#define RTL8367S_SDS_CMD BIT(7)
#define RTL8367S_SDS_RWOP BIT(6)
#define RTL8367S_SDS_INDACS_ADDR_REG 0x6601
#define RTL8367S_SDS_INDACS_DATA_REG 0x6602
#define RTL8367B_NUM_MIB_COUNTERS 58
#define RTL8367S_PHY_ADDR 29
#define RTL8367B_CPU_PORT_NUM 5
#define RTL8367S_CPU_PORT_NUM 7
#define RTL8367B_NUM_PORTS 8
#define RTL8367B_NUM_VLANS 32
#define RTL8367B_NUM_VIDS 4096
@ -255,14 +281,16 @@
#define RTL8367B_PORTS_ALL_BUT_CPU \
(RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 | \
RTL8367B_PORT_E2)
RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 | \
RTL8367B_PORT_E1)
struct rtl8367b_initval {
u16 reg;
u16 val;
};
u32 rtl_device_id;
#define RTL8367B_MIB_RXB_ID 0 /* IfInOctets */
#define RTL8367B_MIB_TXB_ID 28 /* IfOutOctets */
@ -605,6 +633,45 @@ static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {
{0x133E, 0x000E}, {0x133F, 0x0010},
};
static const struct rtl8367b_initval rtl8367c_initvals0[] = {
{0x13c2, 0x0000}, {0x0018, 0x0f00}, {0x0038, 0x0f00}, {0x0058, 0x0f00},
{0x0078, 0x0f00}, {0x0098, 0x0f00}, {0x1d15, 0x0a69}, {0x2000, 0x1340},
{0x2020, 0x1340}, {0x2040, 0x1340}, {0x2060, 0x1340}, {0x2080, 0x1340},
{0x13eb, 0x15bb}, {0x1303, 0x06d6}, {0x1304, 0x0700}, {0x13E2, 0x003F},
{0x13F9, 0x0090}, {0x121e, 0x03CA}, {0x1233, 0x0352}, {0x1237, 0x00a0},
{0x123a, 0x0030}, {0x1239, 0x0084}, {0x0301, 0x1000}, {0x1349, 0x001F},
{0x18e0, 0x4004}, {0x122b, 0x641c}, {0x1305, 0xc000}, {0x1200, 0x7fcb},
{0x0884, 0x0003}, {0x06eb, 0x0001}, {0x00cf, 0xffff}, {0x00d0, 0x0007},
{0x00ce, 0x48b0}, {0x00ce, 0x48b0}, {0x0398, 0xffff}, {0x0399, 0x0007},
{0x0300, 0x0001}, {0x03fa, 0x0007}, {0x08c8, 0x00c0}, {0x0a30, 0x020e},
{0x0800, 0x0000}, {0x0802, 0x0000}, {0x09da, 0x0017}, {0x1d32, 0x0002},
};
static const struct rtl8367b_initval rtl8367s_initvals[] = {
/* Special init for RTL8367SB in RGMII mode with some comments */
/* phy port eee init */
{0x0018, 0x0f00}, {0x1d15, 0x0a69}, {0x2014, 0x0000}, {0x2708, 0x0006},
{0x0038, 0x0f00}, {0x1d15, 0x0a69}, {0x2034, 0x0000}, {0x2748, 0x0006},
{0x0058, 0x0f00}, {0x1d15, 0x0a69}, {0x2054, 0x0000}, {0x2748, 0x0006},
{0x0078, 0x0f00}, {0x1d15, 0x0a69}, {0x2074, 0x0000}, {0x2768, 0x0006},
{0x0018, 0x0f00}, {0x1d15, 0x0a69}, {0x2094, 0x0000}, {0x2788, 0x0006},
/* enable phy 0-4 - after reset phy is disabled */
{0x1d15, 0x0a69}, {0x2000, 0x1340}, {0x2020, 0x1340}, {0x2040, 0x1340},
{0x2060, 0x1340}, {0x2080, 0x1340},
/* standard init */
{0x13eb, 0x15bb}, {0x1303, 0x06d6}, {0x1304, 0x0700}, {0x13E2, 0x003F},
{0x13F9, 0x0090},
/* add init extended interface2 mode == rgmii explicitly */
{0x1303, 0x0767}, {0x1304, 0x7777}, {0x1305, 0xc000}, {0x13E2, 0x01fd},
{0x13c3, 0x0001}, {0x13c4, 0x1076}, {0x13c5, 0x000a},
/*end init ext2 mode*/
{0x121e, 0x03CA}, {0x1233, 0x0352}, {0x1237, 0x00a0}, {0x123a, 0x0030},
{0x1239, 0x0084}, {0x0301, 0x1000}, {0x1349, 0x001F}, {0x18e0, 0x4004},
{0x122b, 0x641c}, {0x1305, 0xc000}, {0x1200, 0x7fcb}, {0x0884, 0x0003},
{0x06eb, 0x0001}, {0x00cf, 0xffff}, {0x00d0, 0x0007}, {0x00ce, 0x48b0},
{0x0398, 0xffff}, {0x0399, 0x0007}, {0x0300, 0x0001}, {0x03fa, 0x0007},
{0x08c8, 0x00c0}, {0x0a30, 0x020e}, {0x0800, 0x0000}, {0x0802, 0x0000},
{0x09da, 0x0017}, {0x1d32, 0x0002}, {0x13c2, 0x0000},
};
static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
const struct rtl8367b_initval *initvals,
int count)
@ -612,6 +679,10 @@ static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
int err;
int i;
if (rtl_device_id == 0x0020) {
return 0;
}
for (i = 0; i < count; i++)
REG_WR(smi, initvals[i].reg, initvals[i].val);
@ -727,6 +798,11 @@ static int rtl8367b_init_regs(struct rtl8366_smi *smi)
rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
RTL8367B_CHIP_VER_RLVID_MASK;
if (of_device_is_compatible(smi->parent->of_node,
"realtek,rtl8367s")) {
initvals = rtl8367s_initvals;
count = ARRAY_SIZE(rtl8367s_initvals);
} else {
switch (rlvid) {
case 0:
initvals = rtl8367r_vb_initvals_0;
@ -742,6 +818,7 @@ static int rtl8367b_init_regs(struct rtl8366_smi *smi)
dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
return -ENODEV;
}
}
/* TODO: disable RLTP */
@ -779,7 +856,45 @@ static int rtl8367b_reset_chip(struct rtl8366_smi *smi)
static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
enum rtl8367_extif_mode mode)
{
int err;
int err, i;
/* for SGMII, works (from rtl8367s_api.c in TL-R600VPN v4 GPL) */
unsigned int redData[][2] = {
{0x7180, 0x2},
{0x04D7, 0x0480},
{0xF994, 0x0481},
{0x31A2, 0x0482},
{0x6960, 0x0483},
{0x9728, 0x0484},
{0x9D85, 0x0423},
{0xD810, 0x0424},
{0x0F80, 0x0001}
};
/*
* for HSGMII, works
* (from rtl8367c_asicdrv_port.c in TL-R600VPN v4 GPL,
* based on redDataHB and customized like redData)
*/
unsigned int redDataH[][2] = {
{0x7180, 0x2},
{0x82F0, 0x0500},
{0xF195, 0x0501},
{0x31A2, 0x0502},
{0x7960, 0x0503},
{0x9728, 0x0504},
{0x9D85, 0x0423},
{0xD810, 0x0424},
{0x0F80, 0x0001},
{0x83F2, 0x002E}
};
if ((mode == RTL8367S_EXTIF_MODE_SGMII ||
mode == RTL8367S_EXTIF_MODE_HSGMII)
&& id != RTL8367_EXTIF1) {
dev_err(smi->parent,
"SGMII/HSGMII mode is only available in extif1\n");
return -EINVAL;
}
/* set port mode */
switch (mode) {
@ -787,7 +902,7 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
RTL8367B_DEBUG0_SEL33(id),
RTL8367B_DEBUG0_SEL33(id));
if (id <= 1) {
if (id <= RTL8367_EXTIF1) {
REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
RTL8367B_DEBUG0_DRI(id) |
RTL8367B_DEBUG0_DRI_RG(id) |
@ -823,6 +938,17 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
RTL8367B_DEBUG0_SEL33(id),
RTL8367B_DEBUG0_SEL33(id));
REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6));
if (of_device_is_compatible(smi->parent->of_node,
"realtek,rtl8367s")) {
REG_RMW(smi, RTL8367S_EXT_TXC_DLY_REG,
RTL8367S_EXT_GMII_TX_DELAY_MASK
<< RTL8367S_EXT1_GMII_TX_DELAY_SHIFT |
RTL8367S_EXT_GMII_TX_DELAY_MASK
<< RTL8367S_EXT0_GMII_TX_DELAY_SHIFT,
5 << RTL8367S_EXT1_GMII_TX_DELAY_SHIFT | /* shoud be configured */
6 << RTL8367S_EXT0_GMII_TX_DELAY_SHIFT); /* in set_rgmii_delay? */
}
break;
case RTL8367_EXTIF_MODE_MII_MAC:
@ -832,13 +958,49 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0);
break;
case RTL8367S_EXTIF_MODE_SGMII:
if (!of_device_is_compatible(smi->parent->of_node,
"realtek,rtl8367s"))
goto invalid_mode;
/* setup SerDes register for SGMII */
for (i = 0; i <= 7; i++) {
REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, redData[i][0]);
REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, redData[i][1]);
REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
}
break;
case RTL8367S_EXTIF_MODE_HSGMII:
if (!of_device_is_compatible(smi->parent->of_node,
"realtek,rtl8367s"))
goto invalid_mode;
/* setup SerDes register for HSGMII */
for (i = 0; i <= 8; i++) {
REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, redDataH[i][0]);
REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, redDataH[i][1]);
REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
}
break;
default:
dev_err(smi->parent,
"invalid mode for external interface %d\n", id);
return -EINVAL;
goto invalid_mode;
}
if (id <= 1)
if (id == RTL8367_EXTIF1 &&
of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s")) {
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_MAC8_SEL_HSGMII_MASK,
(mode == RTL8367S_EXTIF_MODE_HSGMII)
? RTL8367S_CFG_MAC8_SEL_HSGMII_MASK : 0);
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_MAC8_SEL_SGMII,
(mode == RTL8367S_EXTIF_MODE_SGMII)
? RTL8367S_CFG_MAC8_SEL_SGMII : 0);
}
if (id <= RTL8367_EXTIF1)
REG_RMW(smi, RTL8367B_DIS_REG,
RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
mode << RTL8367B_DIS_RGMII_SHIFT(id));
@ -847,7 +1009,20 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
RTL8367B_DIS2_RGMII_MASK << RTL8367B_DIS2_RGMII_SHIFT,
mode << RTL8367B_DIS2_RGMII_SHIFT);
if (mode == RTL8367S_EXTIF_MODE_SGMII ||
mode == RTL8367S_EXTIF_MODE_HSGMII) {
REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, 0x7106);
REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, 0x0003);
REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
}
return 0;
invalid_mode:
dev_err(smi->parent,
"invalid mode for external interface %d\n", id);
return -EINVAL;
}
static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
@ -857,6 +1032,20 @@ static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
u32 val;
int err;
if (id == RTL8367_EXTIF1 &&
of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s")) {
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_FDUP,
pa->duplex ? RTL8367S_CFG_SGMII_FDUP : 0);
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_SPD_MASK,
pa->speed << RTL8367S_CFG_SGMII_SPD_SHIFT);
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_LINK,
pa->link ? RTL8367S_CFG_SGMII_LINK : 0);
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_TXFC,
pa->txpause ? RTL8367S_CFG_SGMII_TXFC : 0);
REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_RXFC,
pa->rxpause ? RTL8367S_CFG_SGMII_RXFC : 0);
}
mask = (RTL8367B_DI_FORCE_MODE |
RTL8367B_DI_FORCE_NWAY |
RTL8367B_DI_FORCE_TXPAUSE |
@ -918,6 +1107,15 @@ static int rtl8367b_extif_init(struct rtl8366_smi *smi, int id,
cfg->rxdelay);
if (err)
return err;
if (of_device_is_compatible(smi->parent->of_node,
"realtek,rtl8367s")) {
/* disable pre-emphasis */
REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, 0x28A0);
REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, 0x0482);
REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
}
}
return 0;
@ -928,6 +1126,7 @@ static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
const char *name)
{
struct rtl8367_extif_config *cfg;
enum rtl8367_port_speed speed;
const __be32 *prop;
int size;
int err;
@ -953,7 +1152,11 @@ static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
cfg->ability.rxpause = be32_to_cpup(prop++);
cfg->ability.link = be32_to_cpup(prop++);
cfg->ability.duplex = be32_to_cpup(prop++);
cfg->ability.speed = be32_to_cpup(prop++);
speed = be32_to_cpup(prop++);
if (of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s") &&
cfg->mode == RTL8367S_EXTIF_MODE_HSGMII)
speed = RTL8367_PORT_SPEED_1000;
cfg->ability.speed = speed;
err = rtl8367b_extif_init(smi, id, cfg);
kfree(cfg);
@ -982,23 +1185,28 @@ static int rtl8367b_setup(struct rtl8366_smi *smi)
/* initialize external interfaces */
if (smi->parent->of_node) {
err = rtl8367b_extif_init_of(smi, 0, "realtek,extif0");
err = rtl8367b_extif_init_of(smi, RTL8367_EXTIF0,
"realtek,extif0");
if (err)
return err;
err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1");
err = rtl8367b_extif_init_of(smi, RTL8367_EXTIF1,
"realtek,extif1");
if (err)
return err;
err = rtl8367b_extif_init_of(smi, 2, "realtek,extif2");
err = rtl8367b_extif_init_of(smi, RTL8367_EXTIF2,
"realtek,extif2");
if (err)
return err;
} else {
err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
err = rtl8367b_extif_init(smi, RTL8367_EXTIF0,
pdata->extif0_cfg);
if (err)
return err;
err = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg);
err = rtl8367b_extif_init(smi, RTL8367_EXTIF1,
pdata->extif1_cfg);
if (err)
return err;
}
@ -1273,12 +1481,16 @@ static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
struct switch_port_link *link)
{
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
u32 data = 0;
u32 data = 0, sds_misc = 0;
u32 speed;
if (port >= RTL8367B_NUM_PORTS)
return -EINVAL;
if (port == 6 &&
of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s"))
rtl8366_smi_read_reg(smi, RTL8367S_SDS_MISC, &sds_misc);
rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
@ -1299,7 +1511,10 @@ static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
link->speed = SWITCH_PORT_SPEED_100;
break;
case 2:
link->speed = SWITCH_PORT_SPEED_1000;
link->speed = (((sds_misc & RTL8367S_CFG_MAC8_SEL_HSGMII_MASK)
>> RTL8367S_CFG_MAC8_SEL_HSGMII_SHIFT) == 1)
? SWITCH_PORT_SPEED_2500
: SWITCH_PORT_SPEED_1000;
break;
default:
link->speed = SWITCH_PORT_SPEED_UNKNOWN;
@ -1543,6 +1758,18 @@ static int rtl8367b_detect(struct rtl8366_smi *smi)
return ret;
}
dev_info(smi->parent,
"found chip num:%04x ver:%04x, mode:%04x\n",
chip_num, chip_ver, chip_mode);
/* rtl8367s: known chip num:6367 ver:00a0, mode:00a0 */
if (of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s")) {
if (chip_ver == 0x00a0)
chip_name = "8367S";
else
goto unknown_chip;
} else {
switch (chip_ver) {
case 0x0020:
case 0x1000:
@ -1552,15 +1779,19 @@ static int rtl8367b_detect(struct rtl8366_smi *smi)
chip_name = "8367R-VB";
break;
default:
dev_err(smi->parent,
"unknown chip num:%04x ver:%04x, mode:%04x\n",
chip_num, chip_ver, chip_mode);
return -ENODEV;
goto unknown_chip;
}
}
dev_info(smi->parent, "RTL%s chip found\n", chip_name);
return 0;
unknown_chip:
dev_err(smi->parent,
"unknown chip num:%04x ver:%04x, mode:%04x\n",
chip_num, chip_ver, chip_mode);
return -ENODEV;
}
static struct rtl8366_smi_ops rtl8367b_smi_ops = {
@ -1599,11 +1830,17 @@ static int rtl8367b_probe(struct platform_device *pdev)
smi->ops = &rtl8367b_smi_ops;
smi->num_ports = RTL8367B_NUM_PORTS;
if (of_property_read_u32(pdev->dev.of_node, "cpu_port", &smi->cpu_port)
|| smi->cpu_port >= smi->num_ports)
|| smi->cpu_port >= smi->num_ports) {
if (of_device_is_compatible(pdev->dev.of_node, "realtek,rtl8367s"))
smi->cpu_port = RTL8367S_CPU_PORT_NUM;
else
smi->cpu_port = RTL8367B_CPU_PORT_NUM;
}
smi->num_vlan_mc = RTL8367B_NUM_VLANS;
smi->mib_counters = rtl8367b_mib_counters;
smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);
if (of_device_is_compatible(pdev->dev.of_node, "realtek,rtl8367s"))
smi->phy_id = RTL8367S_PHY_ADDR;
err = rtl8366_smi_init(smi);
if (err)
@ -1650,6 +1887,7 @@ static void rtl8367b_shutdown(struct platform_device *pdev)
#ifdef CONFIG_OF
static const struct of_device_id rtl8367b_match[] = {
{ .compatible = "realtek,rtl8367b" },
{ .compatible = "realtek,rtl8367s" },
{},
};
MODULE_DEVICE_TABLE(of, rtl8367b_match);

10
target/linux/generic/files/include/linux/rtl8367.h
View File

@ -18,6 +18,8 @@ enum rtl8367_port_speed {
RTL8367_PORT_SPEED_10 = 0,
RTL8367_PORT_SPEED_100,
RTL8367_PORT_SPEED_1000,
RTL8367S_PORT_SPEED_500M,
RTL8367S_PORT_SPEED_2500M,
};
struct rtl8367_port_ability {
@ -30,6 +32,12 @@ struct rtl8367_port_ability {
enum rtl8367_port_speed speed;
};
enum rtl8367_extif {
RTL8367_EXTIF0 = 0,
RTL8367_EXTIF1,
RTL8367_EXTIF2,
};
enum rtl8367_extif_mode {
RTL8367_EXTIF_MODE_DISABLED = 0,
RTL8367_EXTIF_MODE_RGMII,
@ -42,6 +50,8 @@ enum rtl8367_extif_mode {
RTL8367B_EXTIF_MODE_RMII_MAC = 7,
RTL8367B_EXTIF_MODE_RMII_PHY,
RTL8367B_EXTIF_MODE_RGMII_33V,
RTL8367S_EXTIF_MODE_SGMII = 9,
RTL8367S_EXTIF_MODE_HSGMII,
};
struct rtl8367_extif_config {

1
target/linux/generic/files/include/linux/switch.h
View File

@ -45,6 +45,7 @@ enum switch_port_speed {
SWITCH_PORT_SPEED_10 = 10,
SWITCH_PORT_SPEED_100 = 100,
SWITCH_PORT_SPEED_1000 = 1000,
SWITCH_PORT_SPEED_2500 = 2500,
};
struct switch_port_link {

8
target/linux/rockchip/armv8/base-files/etc/board.d/02_network
View File

@ -39,6 +39,11 @@ rockchip_setup_interfaces()
friendlyarm,nanopi-r5s)
ucidef_set_interfaces_lan_wan "eth1 eth2" "eth0"
;;
scensmart,sv901)
ucidef_set_interfaces_lan_wan 'eth0' 'eth1'
ucidef_add_switch "switch0" \
"7@eth0" "0:lan:0" "1:lan:1" "2:lan:2" "3:lan:3" "4:lan:4" "5:lan:5" "6:lan:6"
;;
*)
ucidef_set_interface_lan 'eth0'
;;
@ -96,7 +101,8 @@ rockchip_setup_macs()
friendlyarm,nanopi-r5c|\
sharevdi,h3399pc|\
sharevdi,guangmiao-g4c|\
rocktech,mpc1903)
rocktech,mpc1903|\
scensmart,sv901)
wan_mac=$(generate_mac_from_mmc_cid)
lan_mac=$(macaddr_add "$wan_mac" +1)
;;

965
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-sv901.dts Executable file
View File

@ -0,0 +1,965 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/usb/pd.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
model = "ScenSmart SV901";
compatible = "scensmart,sv901", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;
led-boot = &diy_led;
led-failsafe = &diy_led;
led-running = &work_led;
led-upgrade = &diy_led;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
};
chosen {
stdout-path = "serial2:1500000n8";
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <18000>;
};
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&power_key>;
power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds: gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&work_led_pin>, <&diy_led_pin>;
work_led: led-0 {
label = "work_led";
default-state = "off";
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
};
diy_led: led-1 {
label = "diy_led";
default-state = "off";
gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_HIGH>;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8>;
};
// fixed pcie power_supply
vcc0v9_pcie: vcc0v9-pcie {
compatible = "regulator-fixed";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vcc0v9_pcie";
vin-supply = <&vcc1v8_s3>;
};
// in my board vcc3v0_sd no control by any pin.
vcc3v0_sd: vcc3v0-sd {
compatible = "regulator-fixed";
// enable-active-high;
// gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
// pinctrl-names = "default";
// pinctrl-0 = <&sdmmc0_pwr_h>;
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_sd";
vin-supply = <&vcc3v3_sys>;
};
// actually vcc12v0_pcie vcc3v3_pcie control by the same gpio.
// pcie 12v0
vcc12v0_pcie: vcc12v0-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwr_en>;
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc12v0_pcie";
vin-supply = <&dc_12v>;
};
// pcie 3.3v
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_pcie";
vin-supply = <&vcc12v0_pcie>;
};
// 3g module power supply
vcc3v3_3g: vcc3v3-3g-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_3g_drv>;
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_3g";
};
// 3.3v output by core board.
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_sys";
vin-supply = <&vcc_sys>;
};
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc5v0_typec: vcc5v0-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vcc5v0_typec";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vcc_sys";
vin-supply = <&dc_12v>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
vin-supply = <&vcc_sys>;
};
wireless-bluetooth {
compatible = "bluetooth-platdata";
clocks = <&rk808 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;
//uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart0_rts>;
pinctrl-1 = <&uart0_gpios>;
//BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */
BT,reset_gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */
//BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */
//BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */
status = "okay";
uart0_gpios: uart0-gpios {
rockchip,pins =
<&gpio2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "ap6356s";
sdio_vref = <1800>;
//WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
status = "okay";
};
rtl8367s {
compatible = "realtek,rtl8367s";
cpu_port = <7>;
mii-bus = <&mdio0>;
//realtek,extif1 = <1 0 12 1 1 1 1 1 4>; //rtl8367b_extif_init_of
realtek,extif2 = <1 0 1 1 1 1 1 1 2>;
};
// mdio0: mdio {
// compatible = "virtual,mdio-gpio";
// gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>, /* MDC */
// <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; /* MDIO */
// #address-cells = <1>;
// #size-cells = <0>;
// };
};
&vpu {
status = "okay";
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
//assigned-clock-parents = <&clkin_gmac>;
assigned-clock-parents = <&cru SCLK_MAC>;
assigned-clock-rates = <125000000>;
clock_in_out = "output";
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
&gpu {
status = "okay";
mali-supply = <&vdd_gpu>;
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
pmic,stby-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
pmic,hold-gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &pmic_dvs2 &pmic_stby &pmic_hold>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc_sys>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc1v8_pmu>;
regulators {
vdd_center: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-name = "vdd_center";
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-name = "vdd_cpu_l";
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_dvp: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc2v8_dvp: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sdio: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_sdio";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcca3v0_codec: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcca3v0_codec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc_1v5";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcca1v8_codec: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_codec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_s3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&cpu_b_sleep>;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_cpu_b";
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&gpu_sleep>;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_gpu";
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c1 {
i2c-scl-rising-time-ns = <300>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c4 {
i2c-scl-rising-time-ns = <600>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
};
&i2c7 {
status = "okay";
};
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
status = "okay";
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_cs0>;
//cs-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; /*SPI-CS:PC3 and PA6*/
};
&io_domains {
status = "okay";
bt656-supply = <&vcc1v8_dvp>;
audio-supply = <&vcca1v8_codec>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
};
&pcie_phy {
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
assigned-clock-rates = <100000000>;
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "okay";
vpcie0v9-supply = <&vcc0v9_pcie>;
vpcie1v8-supply = <&vcca1v8_s3>;
vpcie3v3-supply = <&vcc3v3_pcie>;
vpcie12v-supply = <&vcc12v0_pcie>;
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
};
&pinctrl {
buttons {
power_key: power_key {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
work_led_pin: work-led-pin {
rockchip,pins =
<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
diy_led_pin: diy-led-pin {
rockchip,pins =
<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_3g_drv: pcie-3g-drv {
rockchip,pins =
<0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
pmic_dvs2: pmic-dvs2 {
rockchip,pins =
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
};
pmic_stby: pmic-stby {
rockchip,pins =
<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
};
pmic_hold: pmic-hold{
rockchip,pins =
<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
cpu_b_sleep: cpu-b-sleep {
rockchip,pins =
<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
gpu_sleep: gpu-sleep {
rockchip,pins =
<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio {
bt_host_wake_l: bt-host-wake-l {
rockchip,pins =
<0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_reg_on_h: bt-reg-on-h {
/* external pullup to VCC1V8_PMUPLL */
rockchip,pins =
<0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins =
<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
vcc5v0_typec_en: vcc5v0-typec-en {
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdmmc {
sdmmc0_det_l: sdmmc0-det-l {
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
sdmmc0_pwr_h: sdmmc0-pwr-h {
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&saradc {
vref-supply = <&vcca1v8_s3>;
status = "okay";
};
&sdio0 {
/* WiFi & BT combo module Ampak AP6356S */
bus-width = <4>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
/* Power supply */
vqmmc-supply = <&vcc1v8_s3>; /* IO line */
vmmc-supply = <&vcc_sdio>; /* card's power */
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
status = "okay";
vqmmc-supply = <&vcc3v0_sd>;
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&tcphy0 {
status = "okay";
};
&tcphy0_usb3 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
max-speed = <4000000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
};
};
&uart2 {
/* for debug */
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "host";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
&vpu {
status = "okay";
};

10
target/linux/rockchip/image/armv8.mk
View File

@ -261,3 +261,13 @@ define Device/xunlong_orangepi-r1-plus-lts
DEVICE_PACKAGES := kmod-usb-net-rtl8152
endef
TARGET_DEVICES += xunlong_orangepi-r1-plus-lts
define Device/scensmart_sv901
DEVICE_VENDOR := ScenSmart
DEVICE_MODEL := SV901
SOC := rk3399
UBOOT_DEVICE_NAME := scensmart-sv901-rk3399
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-bin | gzip | append-metadata
DEVICE_PACKAGES := kmod-r8168 -urngd kmod-igb-rockchip kmod-nvme
endef
TARGET_DEVICES += scensmart_sv901

63
target/linux/rockchip/patches-5.15/213-rockchip-rk3399-add-support-for-ScenSmart-SV901.patch Executable file
View File

@ -0,0 +1,63 @@
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sv901.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-king3399.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
--- a/drivers/staging/fbtft/fb_st7789v_o.c 2023-01-24 14:22:49.000000000 +0800
+++ b/drivers/staging/fbtft/fb_st7789v.c 2023-02-24 09:09:34.201471285 +0800
@@ -217,6 +217,31 @@ static int init_display(struct fbtft_par
return 0;
}
+
+static void fbtft_set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
+{
+ switch(par->info->var.rotate)
+ {
+ case 0: xs+=53;xe+=53;ys+=40;ye+=40;
+ break;
+ case 90: xs+=40;xe+=40;ys+=53;ye+=53;
+ break;
+ case 180: xs+=53;xe+=53;ys+=40;ye+=40;
+ break;
+ case 270: xs+=40;xe+=40;ys+=53;ye+=53;
+ break;
+ default :
+ break;
+ }
+
+ write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
+ xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
+
+ write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
+ ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
+
+ write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
+}
/*
* write_vmem() - write data to display.
* @par: FBTFT parameter object.
@@ -368,14 +393,15 @@ static int blank(struct fbtft_par *par,
static struct fbtft_display display = {
.regwidth = 8,
- .width = 240,
- .height = 320,
+ .width = 135,
+ .height = 240,
.gamma_num = 2,
.gamma_len = 14,
.gamma = HSD20_IPS_GAMMA,
.fbtftops = {
.init_display = init_display,
.write_vmem = write_vmem,
+ .set_addr_win = fbtft_set_addr_win,
.set_var = set_var,
.set_gamma = set_gamma,
.blank = blank,

63
target/linux/rockchip/patches-6.1/213-rockchip-rk3399-add-support-for-ScenSmart-SV901.patch Executable file
View File

@ -0,0 +1,63 @@
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sv901.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-king3399.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
--- a/drivers/staging/fbtft/fb_st7789v_o.c 2023-01-24 14:22:49.000000000 +0800
+++ b/drivers/staging/fbtft/fb_st7789v.c 2023-02-24 09:09:34.201471285 +0800
@@ -217,6 +217,31 @@ static int init_display(struct fbtft_par
return 0;
}
+
+static void fbtft_set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
+{
+ switch(par->info->var.rotate)
+ {
+ case 0: xs+=53;xe+=53;ys+=40;ye+=40;
+ break;
+ case 90: xs+=40;xe+=40;ys+=53;ye+=53;
+ break;
+ case 180: xs+=53;xe+=53;ys+=40;ye+=40;
+ break;
+ case 270: xs+=40;xe+=40;ys+=53;ye+=53;
+ break;
+ default :
+ break;
+ }
+
+ write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
+ xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
+
+ write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
+ ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
+
+ write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
+}
/*
* write_vmem() - write data to display.
* @par: FBTFT parameter object.
@@ -368,14 +393,15 @@ static int blank(struct fbtft_par *par,
static struct fbtft_display display = {
.regwidth = 8,
- .width = 240,
- .height = 320,
+ .width = 135,
+ .height = 240,
.gamma_num = 2,
.gamma_len = 14,
.gamma = HSD20_IPS_GAMMA,
.fbtftops = {
.init_display = init_display,
.write_vmem = write_vmem,
+ .set_addr_win = fbtft_set_addr_win,
.set_var = set_var,
.set_gamma = set_gamma,
.blank = blank,