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rockchip: add USB3.0 phy support for RK3328

This commit is contained in:
coolsnowwolf 2023-04-11 16:36:24 +08:00
parent e4901141b5
commit f57ce2a85e
3 changed files with 1269 additions and 0 deletions
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1
target/linux/rockchip/armv8/config-5.4
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@ -427,6 +427,7 @@ CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_EMMC=y
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y

1179
target/linux/rockchip/patches-5.4/208--phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch Normal file
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File diff suppressed because it is too large Load Diff

89
target/linux/rockchip/patches-5.4/209-arm64-dts-rk3328-add-usb3phy-nodes-for-rk3328.patch Normal file
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@ -0,0 +1,89 @@
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -56,6 +56,15 @@ vcc_rtl8153: vcc-rtl8153-regulator {
enable-active-high;
};
+ vcc_host_vbus: host-vbus-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_host_vbus";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
@@ -379,6 +388,19 @@ &u2phy_otg {
status = "okay";
};
+&u3phy {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&u3phy_utmi {
+ status = "okay";
+};
+
+&u3phy_pipe {
+ status = "okay";
+};
+
&uart2 {
status = "okay";
};
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -822,6 +822,47 @@
};
};
+ usb3phy_grf: syscon@ff460000 {
+ compatible = "rockchip,usb3phy-grf", "syscon";
+ reg = <0x0 0xff460000 0x0 0x1000>;
+ };
+
+ u3phy: usb3-phy@ff470000 {
+ compatible = "rockchip,rk3328-u3phy";
+ reg = <0x0 0xff470000 0x0 0x0>;
+ rockchip,u3phygrf = <&usb3phy_grf>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
+ clock-names = "u3phy-otg", "u3phy-pipe";
+ resets = <&cru SRST_USB3PHY_U2>,
+ <&cru SRST_USB3PHY_U3>,
+ <&cru SRST_USB3PHY_PIPE>,
+ <&cru SRST_USB3OTG_UTMI>,
+ <&cru SRST_USB3PHY_OTG_P>,
+ <&cru SRST_USB3PHY_PIPE_P>;
+ reset-names = "u3phy-u2-por", "u3phy-u3-por",
+ "u3phy-pipe-mac", "u3phy-utmi-mac",
+ "u3phy-utmi-apb", "u3phy-pipe-apb";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u3phy_utmi: utmi@ff470000 {
+ reg = <0x0 0xff470000 0x0 0x8000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u3phy_pipe: pipe@ff478000 {
+ reg = <0x0 0xff478000 0x0 0x8000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
sdmmc: dwmmc@ff500000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff500000 0x0 0x4000>;