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ramips: mt7621: Fix some cosmetic DTC warnings

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Node /cpus/cpu@0 has a unit name, but no reg property
Node /cpus/cpu@1 has a unit name, but no reg property
Node /cpuintc@0 has a unit name, but no reg property
Node /cpuclock@0 has a unit name, but no reg property
Node /sysclock@0 has a unit name, but no reg property
Node /pcie@1e140000/pcie0 missing ranges for PCI bridge (or not a bridge)
Node /pcie@1e140000/pcie0 missing bus-range for PCI bridge
Node /pcie@1e140000/pcie1 missing ranges for PCI bridge (or not a bridge)
Node /pcie@1e140000/pcie1 missing bus-range for PCI bridge
Node /pcie@1e140000/pcie2 missing ranges for PCI bridge (or not a bridge)
Node /pcie@1e140000/pcie2 missing bus-range for PCI bridge

Signed-off-by: Rosen Penev <rosenp@gmail.com>
This commit is contained in:
Rosen Penev 2018-06-07 14:21:38 -07:00 committed by John Crispin
parent 66cc6dd6c4
commit 289b2f5e85
1 changed files with 10 additions and 9 deletions
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19
target/linux/ramips/dts/mt7621.dtsi
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@ -6,16 +6,23 @@
compatible = "mediatek,mt7621-soc"; compatible = "mediatek,mt7621-soc";
cpus { cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 { cpu@0 {
device_type = "cpu";
compatible = "mips,mips1004Kc"; compatible = "mips,mips1004Kc";
reg = <0x0>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu";
compatible = "mips,mips1004Kc"; compatible = "mips,mips1004Kc";
reg = <0x1>;
}; };
}; };
cpuintc: cpuintc@0 { cpuintc: cpuintc {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;
@ -26,7 +33,7 @@
serial0 = &uartlite; serial0 = &uartlite;
}; };
cpuclock: cpuclock@0 { cpuclock: cpuclock {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
@ -34,7 +41,7 @@
clock-frequency = <880000000>; clock-frequency = <880000000>;
}; };
sysclock: sysclock@0 { sysclock: sysclock {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
@ -457,8 +464,6 @@
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
device_type = "pci";
}; };
pcie1 { pcie1 {
@ -466,8 +471,6 @@
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
device_type = "pci";
}; };
pcie2 { pcie2 {
@ -475,8 +478,6 @@
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
device_type = "pci";
}; };
}; };
}; };