prepare for SPI controller driver
SVN-Revision: 14755
This commit is contained in:
Florian Fainelli
parent
9422b140ba
commit
5e8dfe53b6
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@ -4,6 +4,7 @@
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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* 2009 Florian Fainelli <florian@openwrt.org>
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*/
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#include <linux/kernel.h>
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@ -20,6 +21,9 @@ EXPORT_SYMBOL(bcm63xx_regs_base);
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const int *bcm63xx_irqs;
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EXPORT_SYMBOL(bcm63xx_irqs);
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const unsigned long *bcm63xx_regs_spi;
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EXPORT_SYMBOL(bcm63xx_regs_spi);
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static u16 bcm63xx_cpu_id;
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static u16 bcm63xx_cpu_rev;
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static unsigned int bcm63xx_cpu_freq;
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@ -49,6 +53,21 @@ static const int bcm96338_irqs[] = {
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[IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
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};
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static const unsigned long bcm96338_regs_spi[] = {
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[SPI_CMD] = SPI_BCM_6338_SPI_CMD,
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[SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS,
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[SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST,
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[SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK,
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[SPI_ST] = SPI_BCM_6338_SPI_ST,
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[SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG,
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[SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE,
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[SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL,
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[SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL,
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[SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL,
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[SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA,
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[SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA,
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};
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/*
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* 6348 register sets and irqs
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*/
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@ -90,6 +109,21 @@ static const int bcm96348_irqs[] = {
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[IRQ_PCI] = BCM_6348_PCI_IRQ,
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};
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static const unsigned long bcm96348_regs_spi[] = {
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[SPI_CMD] = SPI_BCM_6348_SPI_CMD,
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[SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS,
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[SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST,
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[SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK,
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[SPI_ST] = SPI_BCM_6348_SPI_ST,
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[SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG,
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[SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE,
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[SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL,
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[SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL,
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[SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL,
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[SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA,
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[SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA,
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};
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/*
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* 6358 register sets and irqs
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*/
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@ -133,6 +167,21 @@ static const int bcm96358_irqs[] = {
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[IRQ_PCI] = BCM_6358_PCI_IRQ,
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};
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static const unsigned long bcm96358_regs_spi[] = {
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[SPI_CMD] = SPI_BCM_6358_SPI_CMD,
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[SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS,
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[SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST,
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[SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK,
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[SPI_ST] = SPI_BCM_6358_SPI_STATUS,
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[SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG,
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[SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE,
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[SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL,
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[SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL,
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[SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL,
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[SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA,
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[SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_FIFO,
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};
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u16 __bcm63xx_get_cpu_id(void)
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{
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return bcm63xx_cpu_id;
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@ -236,16 +285,19 @@ void __init bcm63xx_cpu_init(void)
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expected_cpu_id = BCM6338_CPU_ID;
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bcm63xx_regs_base = bcm96338_regs_base;
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bcm63xx_irqs = bcm96338_irqs;
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bcm63xx_regs_spi = bcm96338_regs_spi;
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break;
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case CPU_BCM6348:
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expected_cpu_id = BCM6348_CPU_ID;
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bcm63xx_regs_base = bcm96348_regs_base;
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bcm63xx_irqs = bcm96348_irqs;
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bcm63xx_regs_spi = bcm96348_regs_spi;
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break;
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case CPU_BCM6358:
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expected_cpu_id = BCM6358_CPU_ID;
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bcm63xx_regs_base = bcm96358_regs_base;
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bcm63xx_irqs = bcm96358_irqs;
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bcm63xx_regs_spi = bcm96358_regs_spi;
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break;
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}
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60
target/linux/brcm63xx/files/arch/mips/bcm63xx/dev-spi.c
Normal file
60
target/linux/brcm63xx/files/arch/mips/bcm63xx/dev-spi.c
Normal file
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@ -0,0 +1,60 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_dev_spi.h>
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static struct resource spi_resources[] = {
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{
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.start = -1, /* filled at runtime */
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.end = -1, /* filled at runtime */
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.flags = IORESOURCE_MEM,
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},
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{
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.start = -1, /* filled at runtime */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct bcm63xx_spi_pdata spi_pdata = {
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.bus_num = 0,
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.num_chipselect = 4,
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.speed_hz = 50000000, /* Fclk */
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};
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static struct platform_device bcm63xx_spi_device = {
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.name = "bcm63xx_spi",
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.id = 0,
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.num_resources = ARRAY_SIZE(spi_resources),
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.resource = spi_resources,
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.dev.pdata = &spi_pdata;
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};
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int __init bcm63xx_spi_register(void)
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{
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spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
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spi_resources[0].end = spi_resources[0].start;
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spi_resources[0].end += RSET_SPI_SIZE - 1;
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spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
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/* Fill in platform data */
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if (CPU_IS_BCM6338() || CPU_IS_BCM6348()) {
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spi_pdata.msg_fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
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spi_pdata.rx_fifo_size = SPI_BCM_6338_SPI_RX_DATA_SIZE;
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}
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if (CPU_IS_BCM6358()) {
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spi_pdata.msg_fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
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spi_pdata.rx_fifo_size = SPI_BCM_6358_SPI_RX_DATA_SIZE;
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}
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return platform_device_register(&bcm63xx_spi_device);
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}
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@ -289,6 +289,120 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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return 0;
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}
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/*
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* SPI register layout is not compatible
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* accross CPU versions but it is software
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* compatible
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*/
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enum bcm63xx_regs_spi {
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SPI_CMD,
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SPI_INT_STATUS,
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SPI_INT_MASK_ST,
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SPI_INT_MASK,
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SPI_ST,
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SPI_CLK_CFG,
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SPI_FILL_BYTE,
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SPI_MSG_TAIL,
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SPI_RX_TAIL,
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SPI_MSG_CTL,
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SPI_MSG_DATA,
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SPI_RX_DATA,
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};
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extern const unsigned long *bcm63xx_regs_spi;
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static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
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{
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#ifdef BCMCPU_RUNTIME_DETECT
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return bcm63xx_regs_spi[reg];
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#else
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#ifdef CONFIG_BCM63XX_CPU_6338
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switch (reg) {
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case SPI_CMD:
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return SPI_BCM_6338_SPI_CMD;
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case SPI_INT_STATUS:
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return SPI_BCM_6338_SPI_INT_STATUS;
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case SPI_INT_MASK_ST:
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return SPI_BCM_6338_SPI_MASK_INT_ST;
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case SPI_INT_MASK:
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return SPI_BCM_6338_SPI_INT_MASK;
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case SPI_ST:
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return SPI_BCM_6338_SPI_ST;
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case SPI_CLK_CFG:
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return SPI_BCM_6338_SPI_CLK_CFG;
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case SPI_FILL_BYTE:
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return SPI_BCM_6338_SPI_FILL_BYTE;
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case SPI_MSG_TAIL:
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return SPI_BCM_6338_SPI_MSG_TAIL;
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case SPI_RX_TAIL:
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return SPI_BCM_6338_SPI_RX_TAIL;
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case SPI_MSG_CTL:
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return SPI_BCM_6338_SPI_MSG_CTL;
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case SPI_MSG_DATA:
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return SPI_BCM_6338_SPI_MSG_DATA;
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case SPI_RX_DATA:
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return SPI_BCM_6338_SPI_RX_DATA;
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}
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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switch (reg) {
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case SPI_CMD:
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return SPI_BCM_6348_SPI_CMD;
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case SPI_INT_MASK_ST:
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return SPI_BCM_6348_SPI_MASK_INT_ST;
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case SPI_INT_STATUS:
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return SPI_BCM_6348_SPI_INT_STATUS;
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case SPI_ST:
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return SPI_BCM_6348_SPI_ST;
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case SPI_CLK_CFG:
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return SPI_BCM_6348_SPI_CLK_CFG;
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case SPI_FILL_BYTE:
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return SPI_BCM_6348_SPI_FILL_BYTE;
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case SPI_MSG_TAIL:
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return SPI_BCM_6348_SPI_MSG_TAIL;
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case SPI_RX_TAIL:
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return SPI_BCM_6348_SPI_RX_TAIL;
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case SPI_MSG_CTL:
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return SPI_BCM_6348_SPI_MSG_CTL;
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case SPI_MSG_DATA:
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return SPI_BCM_6348_SPI_MSG_DATA;
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case SPI_BCM_6348_SPI_RX_DATA:
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return SPI_BCM_6348_SPI_RX_DATA;
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}
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6358
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switch (reg) {
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case SPI_CMD:
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return SPI_BCM_6358_SPI_CMD;
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case SPI_INT_STATUS:
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return SPI_BCM_6358_SPI_INT_STATUS;
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case SPI_INT_MASK_ST:
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return SPI_BCM_6358_SPI_MASK_INT_ST;
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case SPI_INT_MASK:
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return SPI_BCM_6358_SPI_INT_MASK;
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case SPI_ST:
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return SPI_BCM_6358_SPI_STATUS;
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case SPI_CLK_CFG:
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return SPI_BCM_6358_SPI_CLK_CFG;
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case SPI_FILL_BYTE:
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return SPI_BCM_6358_SPI_FILL_BYTE;
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case SPI_MSG_TAIL:
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return SPI_BCM_6358_SPI_MSG_TAIL;
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case SPI_RX_TAIL:
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return SPI_BCM_6358_SPI_RX_TAIL;
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case SPI_MSG_CTL:
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return SPI_BCM_6358_MSG_CTL;
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case SPI_MSG_DATA:
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return SPI_BCM_6358_SPI_MSG_DATA;
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case SPI_RX_DATA:
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return SPI_BCM_6358_SPI_RX_FIFO;
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}
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#endif
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#endif
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return 0;
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}
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/*
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* IRQ number changes across CPU too
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*/
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@ -0,0 +1,16 @@
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#ifndef BCM63XX_DEV_SPI_H
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#define BCM63XX_DEV_SPI_H
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#include <linux/types.h>
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int bcm63xx_spi_register(void);
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struct bcm63xx_spi_pdata {
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unsigned int msg_fifo_size;
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unsigned int rx_fifo_size;
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int bus_num;
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int num_chipselect;
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u32 speed_hz;
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};
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#endif /* BCM63XX_DEV_SPI_H */
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@ -65,6 +65,12 @@
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bcm63xx_regset_address(s) + (o))
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#define bcm_rset_writel(s,v,o) bcm_writel((v), \
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bcm63xx_regset_address(s) + (o))
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#define bcm_reg_spi_readb(s,o) bcm_readb(bcm63xx_spireg(s) + (o))
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#define bcm_reg_spi_readw(s,o) bcm_readw(bcm63xx_spireg(s) + (o))
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#define bcm_reg_spi_writeb(s,v,o) bcm_writeb((v), \
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bcm63xx_spireg(s) + (o))
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#define bcm_reg_spi_writew(s,v,o) bcm_writew((v), \
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bcm63xx_spireg(s) + (o))
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/*
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* helpers for frequently used register sets
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@ -89,5 +95,9 @@
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#define bcm_memc_writel(v,o) bcm_rset_writel(RSET_MEMC, (v), (o))
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#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
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#define bcm_ddr_writel(v,o) bcm_rset_writel(RSET_DDR, (v), (o))
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#define bcm_spi_readb(o) bcm_reg_spi_readb(RSET_SPI, (o))
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#define bcm_spi_readw(o) bcm_reg_spi_readw(RSET_SPI, (o))
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#define bcm_spi_writeb(v,o) bcm_reg_spi_writeb(RSET_SPI, (v), (o))
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#define bcm_spi_writew(v,o) bcm_reg_spi_writew(RSET_SPI, (v), (o))
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#endif /* ! BCM63XX_IO_H_ */
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