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layerscape: add patches for kernel 5.10

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Signed-off-by: Martin Schiller <ms@dev.tdt.de>
This commit is contained in:
Martin Schiller 2021-11-03 13:48:24 +01:00 committed by Hauke Mehrtens
parent 7e35d86ca2
commit 68b4e9fe0e
5 changed files with 12680 additions and 0 deletions
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26
target/linux/layerscape/patches-5.10/300-add-DTS-for-Traverse-LS1043-Boards.patch Normal file
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@ -0,0 +1,26 @@
From 5b35aae22b4ca2400e49561c9267aa01346f91d4 Mon Sep 17 00:00:00 2001
From: Mathew McBride <matt@traverse.com.au>
Date: Tue, 17 Apr 2018 10:01:03 +1000
Subject: [PATCH] add DTS for Traverse LS1043 Boards
Signed-off-by: Mathew McBride <matt@traverse.com.au>
[rebase]
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 3 +++
arch/arm64/boot/dts/freescale/traverse-ls1043s.dts | 29 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/traverse-ls1043v.dts | 29 ++++++++++++++++++++++
3 files changed, 61 insertions(+)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -28,6 +28,9 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043v.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043s.dtb
+
dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb

291
target/linux/layerscape/patches-5.10/301-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch Normal file
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@ -0,0 +1,291 @@
From 55e00e402d6143aeb153761f8144d9fee5f1f009 Mon Sep 17 00:00:00 2001
From: Biwen Li <biwen.li@nxp.com>
Date: Fri, 26 Oct 2018 16:00:37 +0800
Subject: [PATCH] arm: dts: ls1021a: Add LS1021A-IOT board support
Signed-off-by: Biwen Li <biwen.li@nxp.com>
[rebase]
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/ls1021a-iot.dts | 262 ++++++++++++++++++++++++++++++++++++++
2 files changed, 264 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -665,7 +665,8 @@ dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \
ls1021a-tsn.dtb \
- ls1021a-twr.dtb
+ ls1021a-twr.dtb \
+ ls1021a-iot.dtb
dtb-$(CONFIG_SOC_VF610) += \
vf500-colibri-eval-v3.dtb \
vf610-bk4.dtb \
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-iot.dts
@@ -0,0 +1,262 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+ model = "LS1021A IOT Board";
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3p3v: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_2p5v: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker Ext",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ frame-master;
+ bitclock-master;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ frame-master;
+ bitclock-master;
+ };
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&enet0 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy3>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ fixed-link = <0 1 1000 0 0>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
+&can0{
+ status = "disabled";
+};
+
+&can1{
+ status = "disabled";
+};
+
+&can2{
+ status = "disabled";
+};
+
+&can3{
+ status = "okay";
+};
+
+&esdhc{
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ max1239@35 {
+ compatible = "maxim,max1239";
+ reg = <0x35>;
+ #io-channel-cells = <1>;
+ };
+
+ codec: sgtl5000@2a {
+ #sound-dai-cells=<0x0>;
+ compatible = "fsl,sgtl5000";
+ reg = <0x2a>;
+ VDDA-supply = <&reg_3p3v>;
+ VDDIO-supply = <&reg_2p5v>;
+ clocks = <&sys_mclk 1>;
+ };
+
+ pca9555: pca9555@23 {
+ compatible = "nxp,pca9555";
+ /*pinctrl-names = "default";*/
+ /*interrupt-parent = <&gpio2>;
+ interrupts = <19 0x2>;*/
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x23>;
+ };
+
+ ina220@44 {
+ compatible = "ti,ina220";
+ reg = <0x44>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220@45 {
+ compatible = "ti,ina220";
+ reg = <0x45>;
+ shunt-resistor = <1000>;
+ };
+
+ lm75b@48 {
+ compatible = "nxp,lm75a";
+ reg = <0x48>;
+ };
+
+ adt7461a@4c {
+ compatible = "adt7461a";
+ reg = <0x4c>;
+ };
+
+ hdmi: sii9022a@39 {
+ compatible = "fsl,sii902x";
+ reg = <0x39>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
+ };
+};
+
+&i2c1 {
+ status = "disabled";
+};
+
+&ifc {
+ status = "disabled";
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&mdio0 {
+ phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+ tbi1: tbi-phy@1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&qspi {
+ num-cs = <2>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ compatible = "spansion,s25fl129p1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&sai2 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&dcu {
+ display = <&display>;
+ status = "okay";
+
+ display: display@0 {
+ bits-per-pixel = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+
+ timing0: mode0 {
+ clock-frequency = <25000000>;
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <80>;
+ hfront-porch = <80>;
+ vback-porch = <16>;
+ vfront-porch = <16>;
+ hsync-len = <12>;
+ vsync-len = <2>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
+};

295
target/linux/layerscape/patches-5.10/302-arm64-dts-ls1012a-update-with-ppfe-support.patch Normal file
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@ -0,0 +1,295 @@
From 1bb35ff4ce33e65601c8d9c736be52e4aabd6252 Mon Sep 17 00:00:00 2001
From: Calvin Johnson <calvin.johnson@nxp.com>
Date: Sat, 16 Sep 2017 14:20:23 +0530
Subject: [PATCH] arm64: dts: freescale: ls1012a: update with ppfe support
Update ls1012a dtsi and platform dts files with support for ppfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
---
.../boot/dts/freescale/fsl-ls1012a-frdm.dts | 43 +++++++++++++++++
.../boot/dts/freescale/fsl-ls1012a-frwy.dts | 43 +++++++++++++++++
.../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 +++++++++++++++++
.../boot/dts/freescale/fsl-ls1012a-rdb.dts | 47 +++++++++++++++++++
.../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++
5 files changed, 205 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -13,6 +13,11 @@
model = "LS1012A Freedom Board";
compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -74,6 +79,44 @@
};
};
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pfe_mac0: ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ pfe_mac1: ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};
+
&qspi {
status = "okay";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
@@ -14,6 +14,11 @@
/ {
model = "LS1012A FRWY Board";
compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
+
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
};
&duart0 {
@@ -24,6 +29,44 @@
status = "okay";
};
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pfe_mac0: ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ pfe_mac1: ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};
+
&qspi {
status = "okay";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -13,6 +13,11 @@
model = "LS1012A QDS Board";
compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -127,6 +132,44 @@
};
};
};
+
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pfe_mac0: ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x2>;
+ phy-mode = "sgmii-2500";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ pfe_mac1: ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x3>;
+ phy-mode = "sgmii-2500";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};
&qspi {
status = "okay";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -12,6 +12,15 @@
/ {
model = "LS1012A RDB Board";
compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+};
+
+&pcie1 {
+ status = "okay";
};
&duart0 {
@@ -35,6 +44,44 @@
status = "okay";
};
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pfe_mac0: ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ pfe_mac1: ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "rgmii-txid";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};
+
&qspi {
status = "okay";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -531,6 +531,35 @@
};
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ pfe_reserved: packetbuffer@83400000 {
+ reg = <0 0x83400000 0 0xc00000>;
+ };
+ };
+
+ pfe: pfe@04000000 {
+ compatible = "fsl,pfe";
+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
+ reg-names = "pfe", "pfe-ddr";
+ fsl,pfe-num-interfaces = <0x2>;
+ interrupts = <0 172 0x4>, /* HIF interrupt */
+ <0 173 0x4>, /*HIF_NOCPY interrupt */
+ <0 174 0x4>; /* WoL interrupt */
+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
+ memory-region = <&pfe_reserved>;
+ fsl,pfe-scfg = <&scfg 0>;
+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "pfe";
+
+ status = "okay";
+ };
+
firmware {
optee {
compatible = "linaro,optee-tz";

12036
target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch Normal file
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32
target/linux/layerscape/patches-5.10/702-phy-Add-2.5G-SGMII-interface-mode.patch Normal file
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@ -0,0 +1,32 @@
From c918c472546afa83a619ae3cb1a9d7d346c6e288 Mon Sep 17 00:00:00 2001
From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Date: Wed, 29 Nov 2017 15:27:57 +0530
Subject: [PATCH 154/173] phy: Add 2.5G SGMII interface mode
Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII)
in existing phy_interface list
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
include/linux/phy.h | 3 +++
1 file changed, 3 insertions(+)
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -146,6 +146,7 @@ typedef enum {
PHY_INTERFACE_MODE_USXGMII,
/* 10GBASE-KR - with Clause 73 AN */
PHY_INTERFACE_MODE_10GKR,
+ PHY_INTERFACE_MODE_2500SGMII,
PHY_INTERFACE_MODE_MAX,
} phy_interface_t;
@@ -221,6 +222,8 @@ static inline const char *phy_modes(phy_
return "10gbase-kr";
case PHY_INTERFACE_MODE_100BASEX:
return "100base-x";
+ case PHY_INTERFACE_MODE_2500SGMII:
+ return "sgmii-2500";
default:
return "unknown";
}