kernel: bgmac: make it send and receive some packages on BCM4708
This adds some more code for bgmac core rev 4 and it now restarts all cores when initializing the first one on BCM4708. I am just able to send under 100 packages and then DMA TX does not work any more. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 38714
This commit is contained in:
Hauke Mehrtens
parent
b4a01fc854
commit
7444a626e2
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@ -0,0 +1,69 @@
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From 0fc9d696e4855f1e03910c431499d68e75904929 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 10 Nov 2013 20:43:46 +0100
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Subject: [PATCH] bcma: export bcma_find_core_unit()
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---
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drivers/bcma/bcma_private.h | 2 --
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drivers/bcma/main.c | 13 +------------
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include/linux/bcma/bcma.h | 9 ++++++++-
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3 files changed, 9 insertions(+), 15 deletions(-)
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--- a/drivers/bcma/bcma_private.h
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+++ b/drivers/bcma/bcma_private.h
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@@ -33,8 +33,6 @@ int __init bcma_bus_early_register(struc
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int bcma_bus_suspend(struct bcma_bus *bus);
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int bcma_bus_resume(struct bcma_bus *bus);
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#endif
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-struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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- u8 unit);
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/* scan.c */
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int bcma_bus_scan(struct bcma_bus *bus);
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--- a/drivers/bcma/main.c
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+++ b/drivers/bcma/main.c
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@@ -69,18 +69,6 @@ static u16 bcma_cc_core_id(struct bcma_b
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return BCMA_CORE_CHIPCOMMON;
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}
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-struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
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-{
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- struct bcma_device *core;
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-
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- list_for_each_entry(core, &bus->cores, list) {
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- if (core->id.id == coreid)
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- return core;
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- }
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- return NULL;
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-}
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-EXPORT_SYMBOL_GPL(bcma_find_core);
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-
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struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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u8 unit)
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{
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@@ -92,6 +80,7 @@ struct bcma_device *bcma_find_core_unit(
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}
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return NULL;
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}
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+EXPORT_SYMBOL_GPL(bcma_find_core_unit);
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bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
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int timeout)
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--- a/include/linux/bcma/bcma.h
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+++ b/include/linux/bcma/bcma.h
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@@ -418,7 +418,14 @@ static inline void bcma_maskset16(struct
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bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
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}
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-extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
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+extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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+ u8 unit);
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+static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
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+ u16 coreid)
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+{
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+ return bcma_find_core_unit(bus, coreid, 0);
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+}
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+
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extern bool bcma_core_is_enabled(struct bcma_device *core);
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extern void bcma_core_disable(struct bcma_device *core, u32 flags);
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extern int bcma_core_enable(struct bcma_device *core, u32 flags);
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@ -97,6 +97,32 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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}
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/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
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@@ -1488,6 +1512,25 @@ static int bgmac_probe(struct bcma_devic
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goto err_netdev_free;
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}
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+ /* Northstar, take all GMAC cores out of reset */
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+ if (core->id.id == BCMA_CHIP_ID_BCM4707 ||
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+ core->id.id == BCMA_CHIP_ID_BCM53018) {
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+ struct bcma_device *ns_core;
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+ int ns_gmac;
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+
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+ for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
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+ /* As northstar requirement, we have to reset all GAMCs before
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+ * accessing them. et_probe() call pci_enable_device() for etx
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+ * and do si_core_reset for GAMCx only. Then the other three
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+ * GAMCs didn't reset. We do it here.
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+ */
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+ ns_core = bcma_find_core_unit(core->bus, BCMA_CORE_MAC_GBIT, ns_gmac);
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+ if (!bcma_core_is_enabled(ns_core)) {
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+ bcma_core_enable(ns_core, 0);
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+ }
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+ }
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+ }
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+
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bgmac_chip_reset(bgmac);
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err = bgmac_dma_alloc(bgmac);
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--- a/drivers/net/ethernet/broadcom/bgmac.h
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+++ b/drivers/net/ethernet/broadcom/bgmac.h
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@@ -185,6 +185,7 @@
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@ -30,7 +30,7 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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/**************************************************
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* BCMA bus ops
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**************************************************/
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@@ -1542,6 +1554,16 @@ static int bgmac_probe(struct bcma_devic
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@@ -1561,6 +1573,16 @@ static int bgmac_probe(struct bcma_devic
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goto err_dma_free;
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}
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@ -47,7 +47,7 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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err = register_netdev(bgmac->net_dev);
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if (err) {
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bgmac_err(bgmac, "Cannot register net device\n");
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@@ -1571,6 +1593,10 @@ static void bgmac_remove(struct bcma_dev
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@@ -1590,6 +1612,10 @@ static void bgmac_remove(struct bcma_dev
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{
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struct bgmac *bgmac = bcma_get_drvdata(core);
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@ -0,0 +1,163 @@
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From ec12b94d22fa8715561bdffe6da0781dac08423e Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 10 Nov 2013 21:23:57 +0100
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Subject: [PATCH] bgmac: add some workaround for rev 4
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---
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drivers/net/ethernet/broadcom/bgmac.c | 8 ++++----
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drivers/net/ethernet/broadcom/bgmac.h | 4 +++-
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2 files changed, 7 insertions(+), 5 deletions(-)
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--- a/drivers/net/ethernet/broadcom/bgmac.c
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+++ b/drivers/net/ethernet/broadcom/bgmac.c
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@@ -97,6 +97,16 @@ static void bgmac_dma_tx_enable(struct b
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u32 ctl;
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ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
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+ if (bgmac->core->id.rev == 4) {
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+ ctl &= ~BGMAC_DMA_TX_BL_MASK;
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+ ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
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+ ctl &= ~BGMAC_DMA_TX_MR_MASK;
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+ ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
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+ ctl &= ~BGMAC_DMA_TX_PC_MASK;
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+ ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
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+ ctl &= ~BGMAC_DMA_TX_PT_MASK;
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+ ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
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+ }
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ctl |= BGMAC_DMA_TX_ENABLE;
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ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
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bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
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@@ -246,6 +256,17 @@ static void bgmac_dma_rx_enable(struct b
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ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
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ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
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ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
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+
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+ if (bgmac->core->id.rev == 4) {
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+ ctl &= ~BGMAC_DMA_RX_BL_MASK;
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+ ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
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+
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+ ctl &= ~BGMAC_DMA_RX_PC_MASK;
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+ ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
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+
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+ ctl &= ~BGMAC_DMA_RX_PT_MASK;
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+ ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
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+ }
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bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
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}
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@@ -812,13 +833,13 @@ static void bgmac_cmdcfg_maskset(struct
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u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
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u32 new_val = (cmdcfg & mask) | set;
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- bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
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+ bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
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udelay(2);
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if (new_val != cmdcfg || force)
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bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
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- bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
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+ bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
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udelay(2);
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}
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@@ -1029,7 +1050,7 @@ static void bgmac_chip_reset(struct bgma
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BGMAC_CMDCFG_PROM |
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BGMAC_CMDCFG_NLC |
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BGMAC_CMDCFG_CFE |
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- BGMAC_CMDCFG_SR,
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+ BGMAC_CMDCFG_SR(core->id.rev),
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false);
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bgmac_clear_mib(bgmac);
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@@ -1070,7 +1091,7 @@ static void bgmac_enable(struct bgmac *b
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cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
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bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
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- BGMAC_CMDCFG_SR, true);
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+ BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
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udelay(2);
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cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
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bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
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--- a/drivers/net/ethernet/broadcom/bgmac.h
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+++ b/drivers/net/ethernet/broadcom/bgmac.h
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@@ -194,7 +194,9 @@
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#define BGMAC_CMDCFG_TAI 0x00000200
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#define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
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#define BGMAC_CMDCFG_HD_SHIFT 10
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-#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
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+#define BGMAC_CMDCFG_SR_REVO 0x00000800 /* Set to reset mode, for other revs */
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+#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */
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+#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REVO)
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#define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
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#define BGMAC_CMDCFG_AE 0x00400000
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#define BGMAC_CMDCFG_CFE 0x00800000
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@@ -255,9 +257,34 @@
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#define BGMAC_DMA_TX_SUSPEND 0x00000002
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#define BGMAC_DMA_TX_LOOPBACK 0x00000004
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#define BGMAC_DMA_TX_FLUSH 0x00000010
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+#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
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+#define BGMAC_DMA_TX_MR_SHIFT 6
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+#define BGMAC_DMA_TX_MR_1 0
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+#define BGMAC_DMA_TX_MR_2 1
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#define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
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#define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
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#define BGMAC_DMA_TX_ADDREXT_SHIFT 16
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+#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
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+#define BGMAC_DMA_TX_BL_SHIFT 18
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+#define BGMAC_DMA_TX_BL_16 0
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+#define BGMAC_DMA_TX_BL_32 1
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+#define BGMAC_DMA_TX_BL_64 2
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+#define BGMAC_DMA_TX_BL_128 3
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+#define BGMAC_DMA_TX_BL_256 4
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+#define BGMAC_DMA_TX_BL_512 5
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+#define BGMAC_DMA_TX_BL_1024 6
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+#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
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+#define BGMAC_DMA_TX_PC_SHIFT 21
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+#define BGMAC_DMA_TX_PC_0 0
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+#define BGMAC_DMA_TX_PC_4 1
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+#define BGMAC_DMA_TX_PC_8 2
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+#define BGMAC_DMA_TX_PC_16 3
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+#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
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+#define BGMAC_DMA_TX_PT_SHIFT 24
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+#define BGMAC_DMA_TX_PT_1 0
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+#define BGMAC_DMA_TX_PT_2 1
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+#define BGMAC_DMA_TX_PT_4 2
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+#define BGMAC_DMA_TX_PT_8 3
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#define BGMAC_DMA_TX_INDEX 0x04
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#define BGMAC_DMA_TX_RINGLO 0x08
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#define BGMAC_DMA_TX_RINGHI 0x0C
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@@ -285,8 +312,33 @@
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#define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
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#define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
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#define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
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+#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
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+#define BGMAC_DMA_RX_MR_SHIFT 6
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+#define BGMAC_DMA_TX_MR_1 0
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+#define BGMAC_DMA_TX_MR_2 1
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#define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
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#define BGMAC_DMA_RX_ADDREXT_SHIFT 16
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+#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
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+#define BGMAC_DMA_RX_BL_SHIFT 18
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+#define BGMAC_DMA_RX_BL_16 0
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+#define BGMAC_DMA_RX_BL_32 1
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+#define BGMAC_DMA_RX_BL_64 2
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+#define BGMAC_DMA_RX_BL_128 3
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+#define BGMAC_DMA_RX_BL_256 4
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+#define BGMAC_DMA_RX_BL_512 5
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+#define BGMAC_DMA_RX_BL_1024 6
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+#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
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+#define BGMAC_DMA_RX_PC_SHIFT 21
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+#define BGMAC_DMA_RX_PC_0 0
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+#define BGMAC_DMA_RX_PC_4 1
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+#define BGMAC_DMA_RX_PC_8 2
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+#define BGMAC_DMA_RX_PC_16 3
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+#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
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+#define BGMAC_DMA_RX_PT_SHIFT 24
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+#define BGMAC_DMA_RX_PT_1 0
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+#define BGMAC_DMA_RX_PT_2 1
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+#define BGMAC_DMA_RX_PT_4 2
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+#define BGMAC_DMA_RX_PT_8 3
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#define BGMAC_DMA_RX_INDEX 0x24
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#define BGMAC_DMA_RX_RINGLO 0x28
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#define BGMAC_DMA_RX_RINGHI 0x2C
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@ -0,0 +1,69 @@
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From 0fc9d696e4855f1e03910c431499d68e75904929 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 10 Nov 2013 20:43:46 +0100
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Subject: [PATCH] bcma: export bcma_find_core_unit()
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---
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drivers/bcma/bcma_private.h | 2 --
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drivers/bcma/main.c | 13 +------------
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include/linux/bcma/bcma.h | 9 ++++++++-
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3 files changed, 9 insertions(+), 15 deletions(-)
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--- a/drivers/bcma/bcma_private.h
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+++ b/drivers/bcma/bcma_private.h
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@@ -33,8 +33,6 @@ int __init bcma_bus_early_register(struc
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int bcma_bus_suspend(struct bcma_bus *bus);
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int bcma_bus_resume(struct bcma_bus *bus);
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#endif
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-struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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- u8 unit);
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/* scan.c */
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int bcma_bus_scan(struct bcma_bus *bus);
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--- a/drivers/bcma/main.c
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+++ b/drivers/bcma/main.c
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@@ -69,18 +69,6 @@ static u16 bcma_cc_core_id(struct bcma_b
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return BCMA_CORE_CHIPCOMMON;
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}
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-struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
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-{
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- struct bcma_device *core;
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-
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- list_for_each_entry(core, &bus->cores, list) {
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- if (core->id.id == coreid)
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- return core;
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- }
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- return NULL;
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-}
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-EXPORT_SYMBOL_GPL(bcma_find_core);
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-
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struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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u8 unit)
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{
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@@ -92,6 +80,7 @@ struct bcma_device *bcma_find_core_unit(
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}
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return NULL;
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}
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+EXPORT_SYMBOL_GPL(bcma_find_core_unit);
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bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
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int timeout)
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--- a/include/linux/bcma/bcma.h
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+++ b/include/linux/bcma/bcma.h
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@@ -418,7 +418,14 @@ static inline void bcma_maskset16(struct
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bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
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}
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-extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
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+extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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+ u8 unit);
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+static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
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+ u16 coreid)
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+{
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+ return bcma_find_core_unit(bus, coreid, 0);
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+}
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+
|
||||
extern bool bcma_core_is_enabled(struct bcma_device *core);
|
||||
extern void bcma_core_disable(struct bcma_device *core, u32 flags);
|
||||
extern int bcma_core_enable(struct bcma_device *core, u32 flags);
|
||||
|
|
@ -97,6 +97,32 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
|||
}
|
||||
|
||||
/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
|
||||
@@ -1488,6 +1512,25 @@ static int bgmac_probe(struct bcma_devic
|
||||
goto err_netdev_free;
|
||||
}
|
||||
|
||||
+ /* Northstar, take all GMAC cores out of reset */
|
||||
+ if (core->id.id == BCMA_CHIP_ID_BCM4707 ||
|
||||
+ core->id.id == BCMA_CHIP_ID_BCM53018) {
|
||||
+ struct bcma_device *ns_core;
|
||||
+ int ns_gmac;
|
||||
+
|
||||
+ for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
|
||||
+ /* As northstar requirement, we have to reset all GAMCs before
|
||||
+ * accessing them. et_probe() call pci_enable_device() for etx
|
||||
+ * and do si_core_reset for GAMCx only. Then the other three
|
||||
+ * GAMCs didn't reset. We do it here.
|
||||
+ */
|
||||
+ ns_core = bcma_find_core_unit(core->bus, BCMA_CORE_MAC_GBIT, ns_gmac);
|
||||
+ if (!bcma_core_is_enabled(ns_core)) {
|
||||
+ bcma_core_enable(ns_core, 0);
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
bgmac_chip_reset(bgmac);
|
||||
|
||||
err = bgmac_dma_alloc(bgmac);
|
||||
--- a/drivers/net/ethernet/broadcom/bgmac.h
|
||||
+++ b/drivers/net/ethernet/broadcom/bgmac.h
|
||||
@@ -185,6 +185,7 @@
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
|||
/**************************************************
|
||||
* BCMA bus ops
|
||||
**************************************************/
|
||||
@@ -1542,6 +1554,16 @@ static int bgmac_probe(struct bcma_devic
|
||||
@@ -1561,6 +1573,16 @@ static int bgmac_probe(struct bcma_devic
|
||||
goto err_dma_free;
|
||||
}
|
||||
|
||||
|
|
@ -47,7 +47,7 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
|||
err = register_netdev(bgmac->net_dev);
|
||||
if (err) {
|
||||
bgmac_err(bgmac, "Cannot register net device\n");
|
||||
@@ -1571,6 +1593,10 @@ static void bgmac_remove(struct bcma_dev
|
||||
@@ -1590,6 +1612,10 @@ static void bgmac_remove(struct bcma_dev
|
||||
{
|
||||
struct bgmac *bgmac = bcma_get_drvdata(core);
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,163 @@
|
|||
From ec12b94d22fa8715561bdffe6da0781dac08423e Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Sun, 10 Nov 2013 21:23:57 +0100
|
||||
Subject: [PATCH] bgmac: add some workaround for rev 4
|
||||
|
||||
---
|
||||
drivers/net/ethernet/broadcom/bgmac.c | 8 ++++----
|
||||
drivers/net/ethernet/broadcom/bgmac.h | 4 +++-
|
||||
2 files changed, 7 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/broadcom/bgmac.c
|
||||
+++ b/drivers/net/ethernet/broadcom/bgmac.c
|
||||
@@ -97,6 +97,16 @@ static void bgmac_dma_tx_enable(struct b
|
||||
u32 ctl;
|
||||
|
||||
ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
|
||||
+ if (bgmac->core->id.rev == 4) {
|
||||
+ ctl &= ~BGMAC_DMA_TX_BL_MASK;
|
||||
+ ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
|
||||
+ ctl &= ~BGMAC_DMA_TX_MR_MASK;
|
||||
+ ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
|
||||
+ ctl &= ~BGMAC_DMA_TX_PC_MASK;
|
||||
+ ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
|
||||
+ ctl &= ~BGMAC_DMA_TX_PT_MASK;
|
||||
+ ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
|
||||
+ }
|
||||
ctl |= BGMAC_DMA_TX_ENABLE;
|
||||
ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
|
||||
bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
|
||||
@@ -246,6 +256,17 @@ static void bgmac_dma_rx_enable(struct b
|
||||
ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
|
||||
ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
|
||||
ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
|
||||
+
|
||||
+ if (bgmac->core->id.rev == 4) {
|
||||
+ ctl &= ~BGMAC_DMA_RX_BL_MASK;
|
||||
+ ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
|
||||
+
|
||||
+ ctl &= ~BGMAC_DMA_RX_PC_MASK;
|
||||
+ ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
|
||||
+
|
||||
+ ctl &= ~BGMAC_DMA_RX_PT_MASK;
|
||||
+ ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
|
||||
+ }
|
||||
bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
|
||||
}
|
||||
|
||||
@@ -812,13 +833,13 @@ static void bgmac_cmdcfg_maskset(struct
|
||||
u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
|
||||
u32 new_val = (cmdcfg & mask) | set;
|
||||
|
||||
- bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
|
||||
+ bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
|
||||
udelay(2);
|
||||
|
||||
if (new_val != cmdcfg || force)
|
||||
bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
|
||||
|
||||
- bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
|
||||
+ bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
|
||||
udelay(2);
|
||||
}
|
||||
|
||||
@@ -1029,7 +1050,7 @@ static void bgmac_chip_reset(struct bgma
|
||||
BGMAC_CMDCFG_PROM |
|
||||
BGMAC_CMDCFG_NLC |
|
||||
BGMAC_CMDCFG_CFE |
|
||||
- BGMAC_CMDCFG_SR,
|
||||
+ BGMAC_CMDCFG_SR(core->id.rev),
|
||||
false);
|
||||
|
||||
bgmac_clear_mib(bgmac);
|
||||
@@ -1070,7 +1091,7 @@ static void bgmac_enable(struct bgmac *b
|
||||
|
||||
cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
|
||||
bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
|
||||
- BGMAC_CMDCFG_SR, true);
|
||||
+ BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
|
||||
udelay(2);
|
||||
cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
|
||||
bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
|
||||
--- a/drivers/net/ethernet/broadcom/bgmac.h
|
||||
+++ b/drivers/net/ethernet/broadcom/bgmac.h
|
||||
@@ -194,7 +194,9 @@
|
||||
#define BGMAC_CMDCFG_TAI 0x00000200
|
||||
#define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
|
||||
#define BGMAC_CMDCFG_HD_SHIFT 10
|
||||
-#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
|
||||
+#define BGMAC_CMDCFG_SR_REVO 0x00000800 /* Set to reset mode, for other revs */
|
||||
+#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */
|
||||
+#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REVO)
|
||||
#define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
|
||||
#define BGMAC_CMDCFG_AE 0x00400000
|
||||
#define BGMAC_CMDCFG_CFE 0x00800000
|
||||
@@ -255,9 +257,34 @@
|
||||
#define BGMAC_DMA_TX_SUSPEND 0x00000002
|
||||
#define BGMAC_DMA_TX_LOOPBACK 0x00000004
|
||||
#define BGMAC_DMA_TX_FLUSH 0x00000010
|
||||
+#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
|
||||
+#define BGMAC_DMA_TX_MR_SHIFT 6
|
||||
+#define BGMAC_DMA_TX_MR_1 0
|
||||
+#define BGMAC_DMA_TX_MR_2 1
|
||||
#define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
|
||||
#define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
|
||||
#define BGMAC_DMA_TX_ADDREXT_SHIFT 16
|
||||
+#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
|
||||
+#define BGMAC_DMA_TX_BL_SHIFT 18
|
||||
+#define BGMAC_DMA_TX_BL_16 0
|
||||
+#define BGMAC_DMA_TX_BL_32 1
|
||||
+#define BGMAC_DMA_TX_BL_64 2
|
||||
+#define BGMAC_DMA_TX_BL_128 3
|
||||
+#define BGMAC_DMA_TX_BL_256 4
|
||||
+#define BGMAC_DMA_TX_BL_512 5
|
||||
+#define BGMAC_DMA_TX_BL_1024 6
|
||||
+#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
|
||||
+#define BGMAC_DMA_TX_PC_SHIFT 21
|
||||
+#define BGMAC_DMA_TX_PC_0 0
|
||||
+#define BGMAC_DMA_TX_PC_4 1
|
||||
+#define BGMAC_DMA_TX_PC_8 2
|
||||
+#define BGMAC_DMA_TX_PC_16 3
|
||||
+#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
|
||||
+#define BGMAC_DMA_TX_PT_SHIFT 24
|
||||
+#define BGMAC_DMA_TX_PT_1 0
|
||||
+#define BGMAC_DMA_TX_PT_2 1
|
||||
+#define BGMAC_DMA_TX_PT_4 2
|
||||
+#define BGMAC_DMA_TX_PT_8 3
|
||||
#define BGMAC_DMA_TX_INDEX 0x04
|
||||
#define BGMAC_DMA_TX_RINGLO 0x08
|
||||
#define BGMAC_DMA_TX_RINGHI 0x0C
|
||||
@@ -285,8 +312,33 @@
|
||||
#define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
|
||||
#define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
|
||||
#define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
|
||||
+#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
|
||||
+#define BGMAC_DMA_RX_MR_SHIFT 6
|
||||
+#define BGMAC_DMA_TX_MR_1 0
|
||||
+#define BGMAC_DMA_TX_MR_2 1
|
||||
#define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
|
||||
#define BGMAC_DMA_RX_ADDREXT_SHIFT 16
|
||||
+#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
|
||||
+#define BGMAC_DMA_RX_BL_SHIFT 18
|
||||
+#define BGMAC_DMA_RX_BL_16 0
|
||||
+#define BGMAC_DMA_RX_BL_32 1
|
||||
+#define BGMAC_DMA_RX_BL_64 2
|
||||
+#define BGMAC_DMA_RX_BL_128 3
|
||||
+#define BGMAC_DMA_RX_BL_256 4
|
||||
+#define BGMAC_DMA_RX_BL_512 5
|
||||
+#define BGMAC_DMA_RX_BL_1024 6
|
||||
+#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
|
||||
+#define BGMAC_DMA_RX_PC_SHIFT 21
|
||||
+#define BGMAC_DMA_RX_PC_0 0
|
||||
+#define BGMAC_DMA_RX_PC_4 1
|
||||
+#define BGMAC_DMA_RX_PC_8 2
|
||||
+#define BGMAC_DMA_RX_PC_16 3
|
||||
+#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
|
||||
+#define BGMAC_DMA_RX_PT_SHIFT 24
|
||||
+#define BGMAC_DMA_RX_PT_1 0
|
||||
+#define BGMAC_DMA_RX_PT_2 1
|
||||
+#define BGMAC_DMA_RX_PT_4 2
|
||||
+#define BGMAC_DMA_RX_PT_8 3
|
||||
#define BGMAC_DMA_RX_INDEX 0x24
|
||||
#define BGMAC_DMA_RX_RINGLO 0x28
|
||||
#define BGMAC_DMA_RX_RINGHI 0x2C
|
||||
Loading…
Reference in New Issue
Block a user