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ipq806x: 5.15: replace dtsi patches with upstream version

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Reorganize dtsi patches with upstream version and drop dtsi in 5.15
files.
Also add an additional upstream patch for hwspinlock support.
Refresh all the dts with needed changes.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi 2022-06-16 22:12:01 +02:00
parent bd02eb7502
commit 88bf652525
No known key found for this signature in database
GPG Key ID: AC001D09ADBFEAD7
48 changed files with 1618 additions and 1179 deletions
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11
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8062.dtsi"
#include "qcom-ipq8062-smb208.dtsi"
#include <dt-bindings/input/input.h>
/delete-node/ &nand_pins;
@ -134,6 +134,15 @@
};
};
/* nand_pins are used for leds_pins, empty the node
* from ipq8064.dtsi
*/
&nand_pins {
/delete-property/ disable;
/delete-property/ pullups;
/delete-property/ hold;
};
&qcom_pinmux {
pinctrl-0 = <&akro_pins>;
pinctrl-names = "default";

98
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062.dtsi
View File

@ -1,98 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "qcom-ipq8064.dtsi"
/ {
model = "Qualcomm IPQ8062";
compatible = "qcom,ipq8062", "qcom,ipq8064";
aliases {
serial0 = &gsbi4_serial;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
};
&gsbi4 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
serial@16340000 {
status = "okay";
};
/*
* The i2c device on gsbi4 should not be enabled.
* On ipq806x designs gsbi4 i2c is meant for exclusive
* RPM usage. Turning this on in kernel manifests as
* i2c failure for the RPM.
*/
};
&opp_table0 {
/delete-node/opp-1200000000;
/delete-node/opp-1400000000;
/*
* Voltage thresholds are <target min max>
*/
opp-384000000 {
opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>;
opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>;
opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>;
};
opp-600000000 {
opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>;
opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>;
opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>;
};
opp-800000000 {
opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>;
opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>;
};
opp-1000000000 {
opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>;
};
};
&pcie0 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie1 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie2 {
compatible = "qcom,pcie-ipq8064-v2";
};
&smb208_s2a {
regulator-max-microvolt = <1150000>;
};
&smb208_s2b {
regulator-max-microvolt = <1150000>;
};

2
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>

3
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
View File

@ -54,9 +54,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts
View File

@ -25,7 +25,7 @@
};
&qcom_pinmux {
rgmii2_pins: rgmii2_pins {
rgmii2_pins: rgmii2-pins {
mux {
pins = "gpio27", "gpio28", "gpio29",
"gpio30", "gpio31", "gpio32",
@ -66,9 +66,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

8
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
View File

@ -1,4 +1,4 @@
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
@ -234,12 +234,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
@ -37,9 +37,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

81
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts
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@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
@ -158,26 +158,77 @@
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x000e4 0x6a545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
>;
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
qca8k,rgmii56_1_8v;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@4 {
reg = <4>;
label = "lan4";
};
port@5 {
reg = <5>;
label = "wan";
};
/*
port@6 {
reg = <0>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
asym-pause;
};
};
*/
};
};
};
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

3
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
View File

@ -167,9 +167,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
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@ -1,4 +1,4 @@
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
@ -231,9 +231,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

4
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@ -221,8 +221,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
};

69
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
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@ -1,69 +0,0 @@
#include "qcom-ipq8064.dtsi"
/ {
aliases {
serial0 = &gsbi4_serial;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
};
&gsbi4 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
serial@16340000 {
status = "okay";
};
/*
* The i2c device on gsbi4 should not be enabled.
* On ipq806x designs gsbi4 i2c is meant for exclusive
* RPM usage. Turning this on in kernel manifests as
* i2c failure for the RPM.
*/
};
&CPU_SPC {
status = "okay";
};
&pcie0 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie1 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie2 {
compatible = "qcom,pcie-ipq8064-v2";
};
&sata {
ports-implemented = <0x1>;
};
&ss_phy_0 {
qcom,rx-eq = <2>;
qcom,tx-deamp_3_5db = <32>;
qcom,mpll = <5>;
};
&ss_phy_1 {
qcom,rx-eq = <2>;
qcom,tx-deamp_3_5db = <32>;
qcom,mpll = <5>;
};

2
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
View File

@ -1,4 +1,4 @@
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>

2
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
View File

@ -1,4 +1,4 @@
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
View File

@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
@ -159,9 +159,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
cs@0 {
reg = <0>;
compatible = "qcom,nandcs";

6
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
View File

@ -1,4 +1,4 @@
#include "qcom-ipq8065.dtsi"
#include "qcom-ipq8065-smb208.dtsi"
#include <dt-bindings/input/input.h>
@ -108,14 +108,14 @@
};
};
mdio0_pins: mdio0_pins {
mdio0_pins: mdio0-pins {
clk {
pins = "gpio1";
input-disable;
};
};
rgmii2_pins: rgmii2_pins {
rgmii2_pins: rgmii2-pins {
tx {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
input-disable;

9
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi
View File

@ -1,4 +1,4 @@
#include "qcom-ipq8065.dtsi"
#include "qcom-ipq8065-smb208.dtsi"
#include <dt-bindings/input/input.h>
@ -124,14 +124,14 @@
};
};
mdio0_pins: mdio0_pins {
mdio0_pins: mdio0-pins {
clk {
pins = "gpio1";
input-disable;
};
};
rgmii2_pins: rgmii2_pins {
rgmii2_pins: rgmii2-pins {
tx {
pins = "gpio27", "gpio28", "gpio29",
"gpio30", "gpio31", "gpio32";
@ -223,9 +223,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

7
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq8065.dtsi"
#include "qcom-ipq8065-smb208.dtsi"
#include <dt-bindings/input/input.h>
/ {
@ -82,7 +82,7 @@
};
};
rgmii2_pins: rgmii2_pins {
rgmii2_pins: rgmii2-pins {
mux {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
@ -130,9 +130,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

7
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq8065.dtsi"
#include "qcom-ipq8065-smb208.dtsi"
#include <dt-bindings/input/input.h>
/ {
@ -81,7 +81,7 @@
};
};
rgmii2_pins: rgmii2_pins {
rgmii2_pins: rgmii2-pins {
tx {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
input-disable;
@ -119,9 +119,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

167
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065.dtsi
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@ -1,167 +0,0 @@
#include "qcom-ipq8064.dtsi"
/ {
model = "Qualcomm IPQ8065";
compatible = "qcom,ipq8065", "qcom,ipq8064";
aliases {
serial0 = &gsbi4_serial;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
};
&gsbi4 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
serial@16340000 {
status = "okay";
};
/*
* The i2c device on gsbi4 should not be enabled.
* On ipq806x designs gsbi4 i2c is meant for exclusive
* RPM usage. Turning this on in kernel manifests as
* i2c failure for the RPM.
*/
};
&pcie0 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie1 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie2 {
compatible = "qcom,pcie-ipq8064-v2";
};
&sata {
ports-implemented = <0x1>;
};
&smb208_s2a {
regulator-min-microvolt = <775000>;
regulator-max-microvolt = <1275000>;
};
&smb208_s2b {
regulator-min-microvolt = <775000>;
regulator-max-microvolt = <1275000>;
};
&ss_phy_0 {
qcom,rx-eq = <2>;
qcom,tx-deamp_3_5db = <32>;
qcom,mpll = <5>;
};
&ss_phy_1 {
qcom,rx-eq = <2>;
qcom,tx-deamp_3_5db = <32>;
qcom,mpll = <5>;
};
&opp_table_l2 {
/delete-node/opp-1200000000;
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1150000>;
clock-latency-ns = <100000>;
opp-level = <2>;
};
};
&opp_table0 {
/*
* On ipq8065 1.2 ghz freq is not present
* Remove it to make cpufreq work and not
* complain for missing definition
*/
/delete-node/opp-1200000000;
/*
* Voltage thresholds are <target min max>
*/
opp-384000000 {
opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
};
opp-600000000 {
opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
};
opp-800000000 {
opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
};
opp-1000000000 {
opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
};
opp-1400000000 {
opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
opp-level = <1>;
};
opp-1725000000 {
opp-hz = /bits/ 64 <1725000000>;
opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
opp-supported-hw = <0x1>;
clock-latency-ns = <100000>;
opp-level = <2>;
};
};

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
/ {
memory {
@ -140,9 +140,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
compatible = "qcom,nandcs";

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts
View File

@ -1,4 +1,4 @@
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
@ -262,9 +262,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
compatible = "qcom,nandcs";

240
target/linux/ipq806x/patches-5.15/082-ipq8064-dtsi-tweaks.patch
View File

@ -1,240 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -352,6 +352,7 @@
gpio-ranges = <&qcom_pinmux 0 0 69>;
#gpio-cells = <2>;
interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -379,6 +380,7 @@
function = "pcie3_rst";
drive-strength = <12>;
bias-disable;
+ output-low;
};
};
@@ -411,12 +413,9 @@
};
nand_pins: nand_pins {
- mux {
+ disable {
pins = "gpio34", "gpio35", "gpio36",
- "gpio37", "gpio38", "gpio39",
- "gpio40", "gpio41", "gpio42",
- "gpio43", "gpio44", "gpio45",
- "gpio46", "gpio47";
+ "gpio37", "gpio38";
function = "nand";
drive-strength = <10>;
bias-disable;
@@ -424,6 +423,8 @@
pullups {
pins = "gpio39";
+ function = "nand";
+ drive-strength = <10>;
bias-pull-up;
};
@@ -431,6 +432,8 @@
pins = "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45",
"gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
bias-bus-hold;
};
};
@@ -439,6 +442,7 @@
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <3>;
reg = <0x02000000 0x1000>,
<0x02002000 0x1000>;
@@ -468,11 +472,13 @@
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+ clock-output-names = "acpu0_aux";
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+ clock-output-names = "acpu1_aux";
};
adm_dma: dma-controller@18300000 {
@@ -496,13 +502,13 @@
};
saw0: regulator@2089000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
saw1: regulator@2099000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
@@ -530,7 +536,7 @@
status = "disabled";
};
- i2c@124a0000 {
+ gsbi2_i2c: i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
@@ -676,9 +682,6 @@
compatible = "qcom,ipq806x-nand";
reg = <0x1ac00000 0x800>;
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
clocks = <&gcc EBI2_CLK>,
<&gcc EBI2_AON_CLK>;
clock-names = "core", "aon";
@@ -733,10 +736,13 @@
tsens_calib_backup: calib_backup@410 {
reg = <0x410 0xb>;
};
+ speedbin_efuse: speedbin@0c0 {
+ reg = <0x0c0 0x4>;
+ };
};
gcc: clock-controller@900000 {
- compatible = "qcom,gcc-ipq8064";
+ compatible = "qcom,gcc-ipq8064", "syscon";
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -768,10 +774,45 @@
clocks = <&gcc RPM_MSG_RAM_H_CLK>;
clock-names = "ram";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
rpmcc: clock-controller {
compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
#clock-cells = <1>;
};
+
+ regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
};
tcsr: syscon@1a400000 {
@@ -965,7 +1006,7 @@
gmac0: ethernet@37000000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37000000 0x200000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -989,7 +1030,7 @@
gmac1: ethernet@37200000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1013,7 +1054,7 @@
gmac2: ethernet@37400000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1037,7 +1078,7 @@
gmac3: ethernet@37600000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37600000 0x200000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1065,8 +1106,6 @@
clocks = <&gcc USB30_0_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
-
- status = "disabled";
};
ss_phy_0: phy@100f8830 {
@@ -1075,8 +1114,6 @@
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
-
- status = "disabled";
};
usb3_0: usb3@100f8800 {
@@ -1176,7 +1213,7 @@
};
amba: amba {
- compatible = "simple-bus";
+ compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -1195,7 +1232,6 @@
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
- mmc-ddr-1_8v;
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
dma-names = "tx", "rx";

371
target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch
View File

@ -1,371 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -10,6 +10,8 @@
#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mfd/qcom-rpm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
/ {
#address-cells = <1>;
@@ -30,6 +32,16 @@
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
+ clocks = <&kraitcc 0>, <&kraitcc 4>;
+ clock-names = "cpu", "l2";
+ clock-latency = <100000>;
+ cpu-supply = <&smb208_s2a>;
+ operating-points-v2 = <&opp_table0>;
+ voltage-tolerance = <5>;
+ cooling-min-state = <0>;
+ cooling-max-state = <10>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SPC>;
};
cpu1: cpu@1 {
@@ -40,11 +52,125 @@
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
+ clocks = <&kraitcc 1>, <&kraitcc 4>;
+ clock-names = "cpu", "l2";
+ clock-latency = <100000>;
+ cpu-supply = <&smb208_s2b>;
+ operating-points-v2 = <&opp_table0>;
+ voltage-tolerance = <5>;
+ cooling-min-state = <0>;
+ cooling-max-state = <10>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SPC>;
+ };
+
+ idle-states {
+ CPU_SPC: spc {
+ compatible = "qcom,idle-state-spc";
+ status = "disabled";
+ entry-latency-us = <400>;
+ exit-latency-us = <900>;
+ min-residency-us = <3000>;
+ };
};
+ };
- L2: l2-cache {
- compatible = "cache";
- cache-level = <2>;
+ opp_table_l2: opp_table_l2 {
+ compatible = "operating-points-v2";
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <100000>;
+ opp-level = <0>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1150000>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+ };
+
+ opp_table0: opp_table0 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+
+ /*
+ * Voltage thresholds are <target min max>
+ */
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <0>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
};
};
@@ -317,6 +443,15 @@
};
};
+ fab-scaling {
+ compatible = "qcom,fab-scaling";
+ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
+ clock-names = "apps-fab-clk", "ddr-fab-clk";
+ fab_freq_high = <533000000>;
+ fab_freq_nominal = <400000000>;
+ cpu_freq_threshold = <1000000000>;
+ };
+
firmware {
scm {
compatible = "qcom,scm-ipq806x", "qcom,scm";
@@ -384,6 +519,15 @@
};
};
+ i2c4_pins: i2c4_pinmux {
+ mux {
+ pins = "gpio12", "gpio13";
+ function = "gsbi4";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ };
+
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
@@ -437,6 +581,27 @@
bias-bus-hold;
};
};
+
+ mdio0_pins: mdio0_pins {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ rgmii2_pins: rgmii2_pins {
+ mux {
+ pins = "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio32",
+ "gpio51", "gpio52", "gpio59",
+ "gpio60", "gpio61", "gpio62";
+ function = "rgmii2";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
};
intc: interrupt-controller@2000000 {
@@ -513,6 +678,17 @@
regulator;
};
+ saw_l2: regulator@02012000 {
+ compatible = "qcom,saw2", "syscon";
+ reg = <0x02012000 0x1000>;
+ regulator;
+ };
+
+ sic_non_secure: sic-non-secure@12100000 {
+ compatible = "syscon";
+ reg = <0x12100000 0x10000>;
+ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
@@ -637,6 +813,33 @@
};
};
+ gsbi6: gsbi@16500000 {
+ status = "disabled";
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <6>;
+ reg = <0x16500000 0x100>;
+ clocks = <&gcc GSBI6_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ gsbi6_i2c: i2c@16580000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16580000 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
gsbi7: gsbi@16600000 {
status = "disabled";
compatible = "qcom,gsbi-v1.0.0";
@@ -658,6 +861,19 @@
clock-names = "core", "iface";
status = "disabled";
};
+
+ gsbi7_i2c: i2c@16680000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16680000 0x1000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
rng@1a500000 {
@@ -761,6 +977,17 @@
};
};
+ L2: l2-cache {
+ compatible = "qcom,krait-cache", "cache";
+ cache-level = <2>;
+ qcom,saw = <&saw_l2>;
+
+ clocks = <&kraitcc 4>;
+ clock-names = "l2";
+ l2-supply = <&smb208_s1a>;
+ operating-points-v2 = <&opp_table_l2>;
+ };
+
rpm: rpm@108000 {
compatible = "qcom,rpm-ipq8064";
reg = <0x108000 0x1000>;
@@ -828,6 +1055,11 @@
clock-output-names = "acpu_l2_aux";
};
+ kraitcc: clock-controller {
+ compatible = "qcom,krait-cc-v1";
+ #clock-cells = <1>;
+ };
+
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
@@ -835,6 +1067,11 @@
#reset-cells = <1>;
};
+ sfpb_mutex_block: syscon@1200600 {
+ compatible = "syscon";
+ reg = <0x01200600 0x100>;
+ };
+
pcie0: pci@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
@@ -1184,6 +1421,21 @@
};
};
+
+ mdio0: mdio@37000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "qcom,ipq8064-mdio", "syscon";
+ reg = <0x37000000 0x200000>;
+ resets = <&gcc GMAC_CORE1_RESET>;
+ reset-names = "stmmaceth";
+ clocks = <&gcc GMAC_CORE1_CLK>;
+ clock-names = "stmmaceth";
+
+ status = "disabled";
+ };
+
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
@@ -1258,4 +1510,17 @@
};
};
};
+
+ sfpb_mutex: sfpb-mutex {
+ compatible = "qcom,sfpb-mutex";
+ syscon = <&sfpb_mutex_block 4 4>;
+
+ #hwlock-cells = <1>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem>;
+ hwlocks = <&sfpb_mutex 3>;
+ };
};

89
target/linux/ipq806x/patches-5.15/084-ipq8064-v1.0-dtsi-cleanup.patch
View File

@ -1,89 +0,0 @@
This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches
instead of keeping a local version.
We drop partitions, LEDs and keys from the file as we will implement
them differently anyway.
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -42,16 +42,6 @@
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
-
- partition@0 {
- label = "rootfs";
- reg = <0x0 0x1000000>;
- };
-
- partition@1 {
- label = "scratch";
- reg = <0x1000000 0x1000000>;
- };
};
};
};
@@ -64,64 +54,5 @@
ports-implemented = <0x1>;
status = "okay";
};
-
- gpio_keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&buttons_pins>;
- pinctrl-names = "default";
-
- button@1 {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- debounce-interval = <60>;
- };
- button@2 {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- debounce-interval = <60>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&leds_pins>;
- pinctrl-names = "default";
-
- led@7 {
- label = "led_usb1";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "usbdev";
- default-state = "off";
- };
-
- led@8 {
- label = "led_usb3";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "usbdev";
- default-state = "off";
- };
-
- led@9 {
- label = "status_led_fail";
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led@26 {
- label = "sata_led";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led@53 {
- label = "status_led_pass";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
};
};

14
target/linux/ipq806x/patches-5.15/085-ipq8064-v1.0-dtsi-additions.patch
View File

@ -1,14 +0,0 @@
This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches
instead of keeping a local version. This patch adds our local adjustments
for the (local) additional contents of qcom-ipq8064.dtsi
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -56,3 +56,7 @@
};
};
};
+
+&CPU_SPC {
+ status = "okay";
+};

36
target/linux/ipq806x/patches-5.15/103-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed.patch Normal file
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@ -0,0 +1,36 @@
From 5a8aa766cedac0ceaa4beabc30e9fa62dd9f1ac1 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Fri, 29 Apr 2022 14:23:16 +0200
Subject: [PATCH v2 1/2] ARM: dts: qcom: replace gcc PXO with pxo_board fixed
clock
Replace gcc PXO phandle to pxo_board fixed clock declared in the dts.
gcc driver doesn't provide PXO_SRC as it's a fixed-clock. This cause a
kernel panic if any driver actually try to use it.
Fixes: 40cf5c884a96 ("ARM: dts: qcom: add L2CC and RPM for IPQ8064")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -304,7 +304,7 @@
clock-frequency = <25000000>;
};
- pxo_board {
+ pxo_board: pxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
@@ -782,7 +782,7 @@
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
- clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu_l2_aux";
};

39
target/linux/ipq806x/patches-5.15/103-v5.19-02-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-.patch Normal file
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@ -0,0 +1,39 @@
From 9fa82f98cb85e5432060f469253adcf14fa38082 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 17 Jan 2022 21:59:39 +0100
Subject: [PATCH v2 2/2] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc
node for ipq8064
Add syscon compatible required for tsens driver to correctly probe driver
and access the reg. Also add cxo and pxo tag and declare them as gcc clock
now requires them for the ipq8064 gcc driver that has now been modernized.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -298,7 +298,7 @@
};
clocks {
- cxo_board {
+ cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
@@ -736,7 +736,9 @@
};
gcc: clock-controller@900000 {
- compatible = "qcom,gcc-ipq8064";
+ compatible = "qcom,gcc-ipq8064", "syscon";
+ clocks = <&pxo_board>, <&cxo_board>;
+ clock-names = "pxo", "cxo";
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;

101
target/linux/ipq806x/patches-5.15/104-v6.0-01-ARM-dts-qcom-ipq8064-add-multiple-missing-pin-defini.patch Normal file
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@ -0,0 +1,101 @@
From 4af1defb305798d1a064a5ea0d0c9b30e5eee185 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 7 Jul 2022 03:09:35 +0200
Subject: [PATCH 1/8] ARM: dts: qcom: ipq8064: add multiple missing pin
definition
Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4
pins and rgmii2 pins for ipq8064.
Drop i2c4_pins node from ipq8064-ap148 dts as it's now moved to ipq8064
dtsi.
Drop mdio0_pins node from ipq8064-rb3011 dts as it's now moved to
ipq8064 dtsi.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707010943.20857-2-ansuelsmth@gmail.com
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 6 -----
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 9 -------
arch/arm/boot/dts/qcom-ipq8064.dtsi | 32 +++++++++++++++++++++++
3 files changed, 32 insertions(+), 15 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -305,15 +305,6 @@
};
};
- mdio0_pins: mdio0_pins {
- mux {
- pins = "gpio0", "gpio1";
- function = "gpio";
- drive-strength = <8>;
- bias-disable;
- };
- };
-
mdio1_pins: mdio1_pins {
mux {
pins = "gpio10", "gpio11";
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -382,6 +382,13 @@
};
};
+ i2c4_pins: i2c4-default {
+ pins = "gpio12", "gpio13";
+ function = "gsbi4";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
@@ -424,6 +431,8 @@
pullups {
pins = "gpio39";
+ function = "nand";
+ drive-strength = <10>;
bias-pull-up;
};
@@ -431,9 +440,32 @@
pins = "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45",
"gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
bias-bus-hold;
};
};
+
+ mdio0_pins: mdio0-pins {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ rgmii2_pins: rgmii2-pins {
+ mux {
+ pins = "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio32",
+ "gpio51", "gpio52", "gpio59",
+ "gpio60", "gpio61", "gpio62";
+ function = "rgmii2";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
};
intc: interrupt-controller@2000000 {

67
target/linux/ipq806x/patches-5.15/104-v6.0-02-ARM-dts-qcom-ipq8064-add-gsbi6-missing-definition.patch Normal file
View File

@ -0,0 +1,67 @@
From d883a12a547b6d42e795ff3b5ac87cfd013b5423 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 7 Jul 2022 03:09:36 +0200
Subject: [PATCH 2/8] ARM: dts: qcom: ipq8064: add gsbi6 missing definition
Add gsbi6 missing definition for ipq8064.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707010943.20857-3-ansuelsmth@gmail.com
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 43 +++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -663,6 +663,49 @@
};
};
+ gsbi6: gsbi@16500000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x16500000 0x100>;
+ cell-index = <6>;
+ clocks = <&gcc GSBI6_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ status = "disabled";
+
+ gsbi6_i2c: i2c@16580000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16580000 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
+ clock-names = "core", "iface";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ gsbi6_spi: spi@16580000 {
+ compatible = "qcom,spi-qup-v1.1.1";
+ reg = <0x16580000 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
+ clock-names = "core", "iface";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
gsbi7: gsbi@16600000 {
status = "disabled";
compatible = "qcom,gsbi-v1.0.0";

66
target/linux/ipq806x/patches-5.15/104-v6.0-03-ARM-dts-qcom-ipq8064-add-specific-dtsi-with-smb208-r.patch Normal file
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@ -0,0 +1,66 @@
From 5c47a46d5e942ea6b041c8b7727b201817c1ff76 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 7 Jul 2022 03:09:37 +0200
Subject: [PATCH 3/8] ARM: dts: qcom: ipq8064: add specific dtsi with smb208
rpm regulators
Add specific ipq8064 dtsi with smb208 rpm regulators.
Qcom advise to use this configuration but it's not mandatory and OEM
can decide to implement their own regulators.
smb208 regulators are used to scale CPU voltage, L2 cache voltage and
Ubi32 cores.
There regulators are controlled by rpm and to correctly works gsbi4-i2c
require to be NEVER disabled or rpm will reject any regulator change
request.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707010943.20857-4-ansuelsmth@gmail.com
---
arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi | 37 ++++++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8064.dtsi"
+
+&rpm {
+ smb208_regulators: regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
+};

56
target/linux/ipq806x/patches-5.15/104-v6.0-04-ARM-dts-qcom-ipq8064-add-missing-snps-dwmac-compatib.patch Normal file
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@ -0,0 +1,56 @@
From 0ce34e0c13e99c239cce6099f64b0e95697f36b1 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 7 Jul 2022 03:09:38 +0200
Subject: [PATCH 4/8] ARM: dts: qcom: ipq8064: add missing snps,dwmac
compatible for gmac
Add missing snps,dwmac compatible for gmac ipq8064 dtsi.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707010943.20857-5-ansuelsmth@gmail.com
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1042,7 +1042,7 @@
gmac0: ethernet@37000000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37000000 0x200000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1066,7 +1066,7 @@
gmac1: ethernet@37200000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1090,7 +1090,7 @@
gmac2: ethernet@37400000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1114,7 +1114,7 @@
gmac3: ethernet@37600000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37600000 0x200000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";

37
target/linux/ipq806x/patches-5.15/104-v6.0-05-ARM-dts-qcom-ipq8064-disable-usb-phy-by-default.patch Normal file
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@ -0,0 +1,37 @@
From d63d3124c0a5cdbe8b91d81b922fe56b2462e1b9 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 7 Jul 2022 03:09:39 +0200
Subject: [PATCH 5/8] ARM: dts: qcom: ipq8064: disable usb phy by default
Disable usb phy by default. When the usb phy were pushed, half of them
were flagged as disabled by mistake.
Correctly disable all usb phy and enable them only if a device actually
use them.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707010943.20857-6-ansuelsmth@gmail.com
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1188,6 +1188,8 @@
clocks = <&gcc USB30_1_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
+
+ status = "disabled";
};
ss_phy_1: phy@110f8830 {
@@ -1196,6 +1198,8 @@
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
+
+ status = "disabled";
};
usb3_1: usb3@110f8800 {

21
target/linux/ipq806x/patches-5.15/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch → target/linux/ipq806x/patches-5.15/104-v6.0-06-ARM-dts-qcom-ipq8064-reduce-pci-IO-size-to-64K.patch
View File

@ -1,8 +1,10 @@
From 84909e85881d67244240c9f40974ce12a51e3886 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Tue, 11 May 2021 23:09:45 +0200
Subject: [PATCH] ARM: dts: qcom: reduce pci IO size to 64K
From 8fafb7e5c041814876266259e5e439f93571dcef Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 7 Jul 2022 03:09:40 +0200
Subject: [PATCH 6/8] ARM: dts: qcom: ipq8064: reduce pci IO size to 64K
The current value for pci IO is problematic for ath10k wifi card
commonly connected to ipq8064 SoC.
The current value is probably a typo and is actually uncommon to find
1MB IO space even on a x86 arch. Also with recent changes to the pci
driver, pci1 and pci2 now fails to function as any connected device
@ -10,14 +12,17 @@ fails any reg read/write. Reduce this to 64K as it should be more than
enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT
hardcoded for the ARM arch.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707010943.20857-7-ansuelsmth@gmail.com
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1086,7 +1086,7 @@
@@ -885,7 +885,7 @@
#address-cells = <3>;
#size-cells = <2>;
@ -26,7 +31,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
@@ -1137,7 +1137,7 @@
@@ -936,7 +936,7 @@
#address-cells = <3>;
#size-cells = <2>;
@ -35,7 +40,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -1188,7 +1188,7 @@
@@ -987,7 +987,7 @@
#address-cells = <3>;
#size-cells = <2>;

94
target/linux/ipq806x/patches-5.15/104-v6.0-07-ARM-dts-qcom-ipq8064-fix-and-add-some-missing-gsbi-n.patch Normal file
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@ -0,0 +1,94 @@
From 6c421a9c08286389bb331fe783e2625c9efcc187 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 7 Jul 2022 03:09:41 +0200
Subject: [PATCH 7/8] ARM: dts: qcom: ipq8064: fix and add some missing gsbi
node
Add some tag for gsbi to make them usable for ipq8064 SoC. Add missing
gsbi7 i2c node and gsbi1 node.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707010943.20857-8-ansuelsmth@gmail.com
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 54 ++++++++++++++++++++++++++++-
1 file changed, 53 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -539,6 +539,44 @@
regulator;
};
+ gsbi1: gsbi@12440000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x12440000 0x100>;
+ cell-index = <1>;
+ clocks = <&gcc GSBI1_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ status = "disabled";
+
+ gsbi1_serial: serial@12450000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x12450000 0x100>,
+ <0x12400000 0x03>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+
+ status = "disabled";
+ };
+
+ gsbi1_i2c: i2c@12460000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x12460000 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
@@ -562,7 +600,7 @@
status = "disabled";
};
- i2c@124a0000 {
+ gsbi2_i2c: i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
@@ -727,6 +765,20 @@
clock-names = "core", "iface";
status = "disabled";
};
+
+ gsbi7_i2c: i2c@16680000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16680000 0x1000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
+ clock-names = "core", "iface";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
};
rng@1a500000 {

28
target/linux/ipq806x/patches-5.15/104-v6.0-08-ARM-dts-qcom-ipq8064-add-speedbin-efuse-nvmem-node.patch Normal file
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@ -0,0 +1,28 @@
From 7f5aecdd4ffcc018f73171bc0e028cd4e3361acd Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 7 Jul 2022 03:09:43 +0200
Subject: [PATCH 8/8] ARM: dts: qcom: ipq8064: add speedbin efuse nvmem node
Add speedbin efuse nvmem cell needed for the opp table for the CPU
freqs.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707010943.20857-10-ansuelsmth@gmail.com
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++
1 file changed, 3 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -854,6 +854,9 @@
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ speedbin_efuse: speedbin@c0 {
+ reg = <0xc0 0x4>;
+ };
tsens_calib: calib@400 {
reg = <0x400 0xb>;
};

71
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@ -0,0 +1,71 @@
From cdab30b44518513003607ecfc8a22de3dbbb78ed Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 7 Jul 2022 12:20:38 +0200
Subject: [PATCH 1/1] hwspinlock: qcom: Add support for mmio usage to
sfpb-mutex
Allow sfpb-mutex to use mmio in addition to syscon.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707102040.1859-1-ansuelsmth@gmail.com
---
drivers/hwspinlock/qcom_hwspinlock.c | 28 +++++++++++++++++++++++-----
1 file changed, 23 insertions(+), 5 deletions(-)
--- a/drivers/hwspinlock/qcom_hwspinlock.c
+++ b/drivers/hwspinlock/qcom_hwspinlock.c
@@ -19,6 +19,11 @@
#define QCOM_MUTEX_APPS_PROC_ID 1
#define QCOM_MUTEX_NUM_LOCKS 32
+struct qcom_hwspinlock_of_data {
+ u32 offset;
+ u32 stride;
+};
+
static int qcom_hwspinlock_trylock(struct hwspinlock *lock)
{
struct regmap_field *field = lock->priv;
@@ -63,9 +68,20 @@ static const struct hwspinlock_ops qcom_
.unlock = qcom_hwspinlock_unlock,
};
+static const struct qcom_hwspinlock_of_data of_sfpb_mutex = {
+ .offset = 0x4,
+ .stride = 0x4,
+};
+
+/* All modern platform has offset 0 and stride of 4k */
+static const struct qcom_hwspinlock_of_data of_tcsr_mutex = {
+ .offset = 0,
+ .stride = 0x1000,
+};
+
static const struct of_device_id qcom_hwspinlock_of_match[] = {
- { .compatible = "qcom,sfpb-mutex" },
- { .compatible = "qcom,tcsr-mutex" },
+ { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex },
+ { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match);
@@ -112,12 +128,14 @@ static const struct regmap_config tcsr_m
static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev,
u32 *offset, u32 *stride)
{
+ const struct qcom_hwspinlock_of_data *data;
struct device *dev = &pdev->dev;
void __iomem *base;
- /* All modern platform has offset 0 and stride of 4k */
- *offset = 0;
- *stride = 0x1000;
+ data = of_device_get_match_data(dev);
+
+ *offset = data->offset;
+ *stride = data->stride;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))

31
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@ -0,0 +1,31 @@
From fbe4be367b2169602f6a5949a20d2917b25714d4 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 7 Jul 2022 12:20:39 +0200
Subject: [PATCH 1/2] ARM: dts: qcom: ipq8064: add missing hwlock
Add missing hwlock for ipq8064 dtsi provided by qcom,sfpb-mutex.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
[bjorn: Moved the node inside /soc]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707102040.1859-2-ansuelsmth@gmail.com
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1357,5 +1357,12 @@
dma-names = "tx", "rx";
};
};
+
+ sfpb_mutex: hwlock@1200600 {
+ compatible = "qcom,sfpb-mutex";
+ reg = <0x01200600 0x100>;
+
+ #hwlock-cells = <1>;
+ };
};
};

30
target/linux/ipq806x/patches-5.15/105-v6.0-03-ARM-dts-qcom-ipq8064-add-missing-smem-compatible.patch Normal file
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@ -0,0 +1,30 @@
From 4fefb5434c4b735daf913abaef12431405368031 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 7 Jul 2022 12:20:40 +0200
Subject: [PATCH 2/2] ARM: dts: qcom: ipq8064: add missing smem compatible
Add missing smem compatible and hwlocks phandle for ipq8064 dtsi
smem node.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707102040.1859-3-ansuelsmth@gmail.com
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++
1 file changed, 3 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -292,8 +292,11 @@
};
smem: smem@41000000 {
+ compatible = "qcom,smem";
reg = <0x41000000 0x200000>;
no-map;
+
+ hwlocks = <&sfpb_mutex 3>;
};
};

129
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@ -0,0 +1,129 @@
From 9f7097a8b1948533a6db1b53b5c0480cc75bbd16 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 18 Jul 2022 18:05:16 +0200
Subject: [PATCH 1/3] ARM: dts: qcom: ipq8064: add v2 dtsi variant
Add ipq8064-v2.0 dtsi variant that differ from original ipq8064 SoC for
some additional pcie, sata and usb configuration values, additional
reserved memory and serial output.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
.../boot/dts/qcom-ipq8064-v2.0-smb208.dtsi | 37 ++++++++++
arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 +++++++++++++++++++
2 files changed, 106 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8064-v2.0.dtsi"
+
+&rpm {
+ smb208_regulators: regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
+};
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8064.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8064-v2.0";
+
+ aliases {
+ serial0 = &gsbi4_serial;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd@41200000 {
+ reg = <0x41200000 0x300000>;
+ no-map;
+ };
+ };
+};
+
+&gsbi4 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+
+ serial@16340000 {
+ status = "okay";
+ };
+ /*
+ * The i2c device on gsbi4 should not be enabled.
+ * On ipq806x designs gsbi4 i2c is meant for exclusive
+ * RPM usage. Turning this on in kernel manifests as
+ * i2c failure for the RPM.
+ */
+};
+
+&pcie0 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie1 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie2 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&sata {
+ ports-implemented = <0x1>;
+};
+
+&ss_phy_0 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
+
+&ss_phy_1 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};

67
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@ -0,0 +1,67 @@
From 41d9fa8de7845bd92d9c963196fdfd7ea9232bb2 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 18 Jul 2022 18:07:26 +0200
Subject: [PATCH 2/3] ARM: dts: qcom: ipq8064: add ipq8062 variant
ipq8062 SoC is based on ipq8064-v2.0 with lower supported freq, lack of
usb port and a reduced voltage output with the smb208 regulators.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi | 37 ++++++++++++++++++++++
arch/arm/boot/dts/qcom-ipq8062.dtsi | 8 +++++
2 files changed, 45 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
create mode 100644 arch/arm/boot/dts/qcom-ipq8062.dtsi
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "qcom-ipq8062.dtsi"
+
+&rpm {
+ smb208_regulators: regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
+};
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "qcom-ipq8064-v2.0.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8062";
+ compatible = "qcom,ipq8062", "qcom,ipq8064";
+};

67
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@ -0,0 +1,67 @@
From 01e7aa3fe6f76f7960f2382038136235eee9c6cd Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 18 Jul 2022 18:09:35 +0200
Subject: [PATCH 3/3] ARM: dts: qcom: ipq8064: add ipq8065 variant
ipq8065 SoC is based on ipq8064-v2.0 with a more clocked CPU and
an increased voltage output with the smb208 regulators.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi | 37 ++++++++++++++++++++++
arch/arm/boot/dts/qcom-ipq8065.dtsi | 8 +++++
2 files changed, 45 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8065.dtsi"
+
+&rpm {
+ smb208_regulators: regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1275000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1275000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
+};
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8064-v2.0.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8065";
+ compatible = "qcom,ipq8065", "qcom,ipq8064";
+};

95
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@ -0,0 +1,95 @@
From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 17 Jan 2022 23:39:34 +0100
Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for
ipq8064
Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
for the secondary mux.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -301,6 +301,12 @@
};
clocks {
+// qsb: qsb {
+// compatible = "fixed-clock";
+// clock-frequency = <384000000>;
+// #clock-cells = <0>;
+// };
+
cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -503,11 +509,19 @@
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+ clock-output-names = "acpu0_aux";
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ #clock-cells = <0>;
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+ clock-output-names = "acpu1_aux";
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ #clock-cells = <0>;
};
adm_dma: dma-controller@18300000 {
@@ -531,17 +545,23 @@
};
saw0: regulator@2089000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
saw1: regulator@2099000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
+ saw_l2: regulator@02012000 {
+ compatible = "qcom,saw2", "syscon";
+ reg = <0x02012000 0x1000>;
+ regulator;
+ };
+
gsbi1: gsbi@12440000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x12440000 0x100>;
@@ -920,6 +940,17 @@
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu_l2_aux";
+ #clock-cells = <0>;
+ };
+
+ kraitcc: clock-controller {
+ compatible = "qcom,krait-cc-v1";
+ clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
+ <&acc0>, <&acc1>, <&l2cc>; // <&qsb>
+ clock-names = "hfpll0", "hfpll1", "hfpll_l2",
+ "acpu0_aux", "acpu1_aux", "acpu_l2_aux";
+// "qsb";
+ #clock-cells = <1>;
};
lcc: clock-controller@28000000 {

268
target/linux/ipq806x/patches-5.15/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch Normal file
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@ -0,0 +1,268 @@
From 076ebb6e1799c4c7a1d2e07510d88b9e9b57b551 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Tue, 18 Jan 2022 00:03:47 +0100
Subject: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for
ipq8064
Add opp table for cpu and l2 cache. While the current cpufreq is
the generic one that doesn't scale the L2 cache, we add the l2
cache opp anyway for the sake of completeness. This will be handy in the
future when a dedicated cpufreq driver is introduced for krait cores
that will correctly scale l2 cache with the core freq.
Opp-level is set based on the logic of
0: idle level
1: normal level
2: turbo level
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -48,6 +48,105 @@
};
};
+ opp_table_l2: opp_table_l2 {
+ compatible = "operating-points-v2";
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <100000>;
+ opp-level = <0>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1150000>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+ };
+
+ opp_table0: opp_table0 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+
+ /*
+ * Voltage thresholds are <target min max>
+ */
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <0>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+ };
+
thermal-zones {
tsens_tz_sensor0 {
polling-delay-passive = <0>;
--- a/arch/arm/boot/dts/qcom-ipq8065.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
@@ -6,3 +6,92 @@
model = "Qualcomm Technologies, Inc. IPQ8065";
compatible = "qcom,ipq8065", "qcom,ipq8064";
};
+
+&opp_table_l2 {
+ /delete-node/opp-1200000000;
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <1150000>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+};
+
+&opp_table0 {
+ /*
+ * On ipq8065 1.2 ghz freq is not present
+ * Remove it to make cpufreq work and not
+ * complain for missing definition
+ */
+
+ /delete-node/opp-1200000000;
+
+ /*
+ * Voltage thresholds are <target min max>
+ */
+ opp-384000000 {
+ opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
+ opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
+ };
+
+ opp-600000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
+ opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
+ };
+
+ opp-800000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
+ };
+
+ opp-1000000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
+ };
+
+ opp-1400000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
+ opp-level = <1>;
+ };
+
+ opp-1725000000 {
+ opp-hz = /bits/ 64 <1725000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
+ opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
+ opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+};
--- a/arch/arm/boot/dts/qcom-ipq8062.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi
@@ -6,3 +6,39 @@
model = "Qualcomm Technologies, Inc. IPQ8062";
compatible = "qcom,ipq8062", "qcom,ipq8064";
};
+
+&opp_table0 {
+ /delete-node/opp-1200000000;
+ /delete-node/opp-1400000000;
+
+ /*
+ * Voltage thresholds are <target min max>
+ */
+ opp-384000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>;
+ opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>;
+ opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>;
+ };
+
+ opp-600000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>;
+ opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>;
+ };
+
+ opp-800000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>;
+ opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>;
+ };
+
+ opp-1000000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>;
+ };
+};

153
target/linux/ipq806x/patches-5.15/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch Normal file
View File

@ -0,0 +1,153 @@
From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Tue, 18 Jan 2022 00:07:57 +0100
Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu
and l2 for ipq8064
Add multiple binding for cpu node, l2 node and add idle-states
definition for ipq8064 dtsi.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -30,6 +30,15 @@
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
+ clocks = <&kraitcc 0>, <&kraitcc 4>;
+ clock-names = "cpu", "l2";
+ clock-latency = <100000>;
+ operating-points-v2 = <&opp_table0>;
+ voltage-tolerance = <5>;
+ cooling-min-state = <0>;
+ cooling-max-state = <10>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SPC>;
};
cpu1: cpu@1 {
@@ -40,11 +49,35 @@
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
+ clocks = <&kraitcc 1>, <&kraitcc 4>;
+ clock-names = "cpu", "l2";
+ clock-latency = <100000>;
+ operating-points-v2 = <&opp_table0>;
+ voltage-tolerance = <5>;
+ cooling-min-state = <0>;
+ cooling-max-state = <10>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SPC>;
+ };
+
+ idle-states {
+ CPU_SPC: spc {
+ compatible = "qcom,idle-state-spc";
+ status = "disabled";
+ entry-latency-us = <400>;
+ exit-latency-us = <900>;
+ min-residency-us = <3000>;
+ };
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
+ qcom,saw = <&saw_l2>;
+
+ clocks = <&kraitcc 4>;
+ clock-names = "l2";
+ operating-points-v2 = <&opp_table_l2>;
};
};
--- a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
@@ -2,6 +2,18 @@
#include "qcom-ipq8064.dtsi"
+&cpu0 {
+ cpu-supply = <&smb208_s2a>;
+};
+
+&cpu1 {
+ cpu-supply = <&smb208_s2b>;
+};
+
+&L2 {
+ l2-supply = <&smb208_s1a>;
+};
+
&rpm {
smb208_regulators: regulators {
compatible = "qcom,rpm-smb208-regulators";
--- a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
@@ -2,6 +2,18 @@
#include "qcom-ipq8064-v2.0.dtsi"
+&cpu0 {
+ cpu-supply = <&smb208_s2a>;
+};
+
+&cpu1 {
+ cpu-supply = <&smb208_s2b>;
+};
+
+&L2 {
+ l2-supply = <&smb208_s1a>;
+};
+
&rpm {
smb208_regulators: regulators {
compatible = "qcom,rpm-smb208-regulators";
--- a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
@@ -2,6 +2,18 @@
#include "qcom-ipq8062.dtsi"
+&cpu0 {
+ cpu-supply = <&smb208_s2a>;
+};
+
+&cpu1 {
+ cpu-supply = <&smb208_s2b>;
+};
+
+&L2 {
+ l2-supply = <&smb208_s1a>;
+};
+
&rpm {
smb208_regulators: regulators {
compatible = "qcom,rpm-smb208-regulators";
--- a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
@@ -2,6 +2,18 @@
#include "qcom-ipq8065.dtsi"
+&cpu0 {
+ cpu-supply = <&smb208_s2a>;
+};
+
+&cpu1 {
+ cpu-supply = <&smb208_s2b>;
+};
+
+&L2 {
+ l2-supply = <&smb208_s1a>;
+};
+
&rpm {
smb208_regulators: regulators {
compatible = "qcom,rpm-smb208-regulators";

29
target/linux/ipq806x/patches-5.15/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch Normal file
View File

@ -0,0 +1,29 @@
From 6c94e0184e56f9e9f1f5d5f54b20758433e498d2 Mon Sep 17 00:00:00 2001
From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
Date: Wed, 15 Jun 2022 16:47:09 +0200
Subject: [PATCH 1/2] ARM: dts: qcom: fix wrong nad_pins definition for ipq806x
Fix wrong nand_pings definition for bias-disable pins.
Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -559,12 +559,9 @@
};
nand_pins: nand_pins {
- mux {
+ disable {
pins = "gpio34", "gpio35", "gpio36",
- "gpio37", "gpio38", "gpio39",
- "gpio40", "gpio41", "gpio42",
- "gpio43", "gpio44", "gpio45",
- "gpio46", "gpio47";
+ "gpio37", "gpio38";
function = "nand";
drive-strength = <10>;
bias-disable;

45
target/linux/ipq806x/patches-5.15/086-ipq8064-fix-duplicate-node.patch → target/linux/ipq806x/patches-5.15/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch
View File

@ -1,3 +1,18 @@
From 504188183408fac0f61b59f5ed8ea1773fe43669 Mon Sep 17 00:00:00 2001
From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
Date: Wed, 15 Jun 2022 16:59:30 +0200
Subject: [PATCH 2/2] ARM: dts: qcom: add MDIO dedicated controller node for
ipq806x
Add MDIO dedicated controller attached to gmac0 and fix rb3011 dts to
correctly use the new tag.
Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
---
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 134 +++++++++++-----------
arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 +++
2 files changed, 81 insertions(+), 67 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -24,73 +24,6 @@
@ -74,12 +89,17 @@
mdio1: mdio-1 {
status = "okay";
compatible = "virtual,mdio-gpio";
@@ -220,6 +153,68 @@
@@ -220,6 +153,73 @@
status = "okay";
};
+&mdio0 {
+ status = "okay";
+ compatible = "virtual,mdio-gpio";
+ gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
+ <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-0 = <&mdio0_pins>;
+ pinctrl-names = "default";
@ -143,3 +163,26 @@
&gmac0 {
status = "okay";
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1446,6 +1446,20 @@
};
};
+ mdio0: mdio@37000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "qcom,ipq8064-mdio", "syscon";
+ reg = <0x37000000 0x200000>;
+ resets = <&gcc GMAC_CORE1_RESET>;
+ reset-names = "stmmaceth";
+ clocks = <&gcc GMAC_CORE1_CLK>;
+ clock-names = "stmmaceth";
+
+ status = "disabled";
+ };
+
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";

44
target/linux/ipq806x/patches-5.15/851-add-gsbi1-dts.patch
View File

@ -1,44 +0,0 @@
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -689,6 +689,41 @@
reg = <0x12100000 0x10000>;
};
+ gsbi1: gsbi@12440000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <1>;
+ reg = <0x12440000 0x100>;
+ clocks = <&gcc GSBI1_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ syscon-tcsr = <&tcsr>;
+
+ gsbi1_serial: serial@12450000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x12450000 0x100>,
+ <0x12400000 0x03>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ gsbi1_i2c: i2c@12460000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x12460000 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;