bcm47xx: Add support for brcmnand controller on BCMA bus
Back port the patches being submitted upstream in order to make the NAND controller work on BCM47187/5358. This is a prerequisite for supporting devices like the Netgear WNR3500L V2. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This commit is contained in:
Florian Fainelli
parent
cd3de51bb4
commit
acff8aec0c
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@ -147,8 +147,11 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MTD_BCM47XXSFLASH=y
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CONFIG_MTD_BCM47XX_PARTS=y
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_CORE=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_NAND_BCM47XXNFLASH=y
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CONFIG_MTD_NAND_BRCMNAND=y
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CONFIG_MTD_NAND_BRCMNAND_BCMA=y
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CONFIG_MTD_NAND_ECC=y
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CONFIG_MTD_PARSER_TRX=y
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CONFIG_MTD_PHYSMAP=y
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@ -0,0 +1,33 @@
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From: Florian Fainelli <f.fainelli@gmail.com>
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Subject: [PATCH v3 1/9] mtd: rawnand: brcmnand: Assign soc as early as possible
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Date: Fri, 07 Jan 2022 10:46:06 -0800
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Content-Type: text/plain; charset="utf-8"
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In order to key off the brcmnand_probe() code in subsequent changes
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depending upon ctrl->soc, assign that variable as early as possible,
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instead of much later when we have checked that it is non-NULL.
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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drivers/mtd/nand/raw/brcmnand/brcmnand.c | 3 +--
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1 file changed, 1 insertion(+), 2 deletions(-)
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -2949,6 +2949,7 @@ int brcmnand_probe(struct platform_devic
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dev_set_drvdata(dev, ctrl);
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ctrl->dev = dev;
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+ ctrl->soc = soc;
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init_completion(&ctrl->done);
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init_completion(&ctrl->dma_done);
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@@ -3089,8 +3090,6 @@ int brcmnand_probe(struct platform_devic
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* interesting ways
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*/
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if (soc) {
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- ctrl->soc = soc;
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-
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ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
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DRV_NAME, ctrl);
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@ -0,0 +1,150 @@
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From: Florian Fainelli <f.fainelli@gmail.com>
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Subject: [PATCH v3 2/9] mtd: rawnand: brcmnand: Allow SoC to provide I/O operations
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Date: Fri, 07 Jan 2022 10:46:07 -0800
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Content-Type: text/plain; charset="utf-8"
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Allow a brcmnand_soc instance to provide a custom set of I/O operations
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which we will require when using this driver on a BCMA bus which is not
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directly memory mapped I/O. Update the nand_{read,write}_reg accordingly
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to use the SoC operations if provided.
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To minimize the penalty on other SoCs which do support standard MMIO
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accesses, we use a static key which is disabled by default and gets
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enabled if a soc implementation does provide I/O operations.
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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drivers/mtd/nand/raw/brcmnand/brcmnand.c | 28 +++++++++++++++++++++--
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drivers/mtd/nand/raw/brcmnand/brcmnand.h | 29 ++++++++++++++++++++++++
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2 files changed, 55 insertions(+), 2 deletions(-)
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -25,6 +25,7 @@
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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+#include <linux/static_key.h>
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#include <linux/list.h>
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#include <linux/log2.h>
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@@ -207,6 +208,8 @@ enum {
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struct brcmnand_host;
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+static DEFINE_STATIC_KEY_FALSE(brcmnand_soc_has_ops_key);
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+
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struct brcmnand_controller {
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struct device *dev;
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struct nand_controller controller;
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@@ -589,15 +592,25 @@ enum {
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INTFC_CTLR_READY = BIT(31),
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};
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+static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)
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+{
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+ return static_branch_unlikely(&brcmnand_soc_has_ops_key);
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+}
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+
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static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
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{
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+ if (brcmnand_non_mmio_ops(ctrl))
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+ return brcmnand_soc_read(ctrl->soc, offs);
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return brcmnand_readl(ctrl->nand_base + offs);
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}
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static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
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u32 val)
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{
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- brcmnand_writel(val, ctrl->nand_base + offs);
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+ if (brcmnand_non_mmio_ops(ctrl))
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+ brcmnand_soc_write(ctrl->soc, val, offs);
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+ else
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+ brcmnand_writel(val, ctrl->nand_base + offs);
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}
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static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
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@@ -763,13 +776,18 @@ static inline void brcmnand_rmw_reg(stru
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static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
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{
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+ if (brcmnand_non_mmio_ops(ctrl))
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+ return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR);
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return __raw_readl(ctrl->nand_fc + word * 4);
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}
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static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
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int word, u32 val)
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{
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- __raw_writel(val, ctrl->nand_fc + word * 4);
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+ if (brcmnand_non_mmio_ops(ctrl))
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+ brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR);
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+ else
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+ __raw_writel(val, ctrl->nand_fc + word * 4);
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}
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static inline void edu_writel(struct brcmnand_controller *ctrl,
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@@ -2951,6 +2969,12 @@ int brcmnand_probe(struct platform_devic
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ctrl->dev = dev;
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ctrl->soc = soc;
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+ /* Enable the static key if the soc provides I/O operations indicating
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+ * that a non-memory mapped IO access path must be used
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+ */
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+ if (brcmnand_soc_has_ops(ctrl->soc))
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+ static_branch_enable(&brcmnand_soc_has_ops_key);
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+
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init_completion(&ctrl->done);
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init_completion(&ctrl->dma_done);
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init_completion(&ctrl->edu_done);
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.h
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.h
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@@ -11,12 +11,25 @@
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struct platform_device;
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struct dev_pm_ops;
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+struct brcmnand_io_ops;
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+
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+/* Special register offset constant to intercept a non-MMIO access
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+ * to the flash cache register space. This is intentionally large
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+ * not to overlap with an existing offset.
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+ */
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+#define BRCMNAND_NON_MMIO_FC_ADDR 0xffffffff
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struct brcmnand_soc {
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bool (*ctlrdy_ack)(struct brcmnand_soc *soc);
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void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
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void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
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bool is_param);
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+ const struct brcmnand_io_ops *ops;
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+};
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+
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+struct brcmnand_io_ops {
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+ u32 (*read_reg)(struct brcmnand_soc *soc, u32 offset);
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+ void (*write_reg)(struct brcmnand_soc *soc, u32 val, u32 offset);
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};
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static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc,
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@@ -58,6 +71,22 @@ static inline void brcmnand_writel(u32 v
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writel_relaxed(val, addr);
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}
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+static inline bool brcmnand_soc_has_ops(struct brcmnand_soc *soc)
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+{
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+ return soc && soc->ops && soc->ops->read_reg && soc->ops->write_reg;
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+}
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+
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+static inline u32 brcmnand_soc_read(struct brcmnand_soc *soc, u32 offset)
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+{
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+ return soc->ops->read_reg(soc, offset);
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+}
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+
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+static inline void brcmnand_soc_write(struct brcmnand_soc *soc, u32 val,
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+ u32 offset)
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+{
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+ soc->ops->write_reg(soc, val, offset);
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+}
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+
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int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc);
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int brcmnand_remove(struct platform_device *pdev);
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@ -0,0 +1,52 @@
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From: Florian Fainelli <f.fainelli@gmail.com>
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Subject: [PATCH v3 3/9] mtd: rawnand: brcmnand: Avoid pdev in brcmnand_init_cs()
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Date: Fri, 07 Jan 2022 10:46:08 -0800
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Content-Type: text/plain; charset="utf-8"
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In preparation for encapsulating more of what the loop calling
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brcmnand_init_cs() does, avoid using platform_device when it is the
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device behind platform_device that we are using for printing errors.
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No functional changes introduced.
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -2722,7 +2722,7 @@ static const struct nand_controller_ops
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static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
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{
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struct brcmnand_controller *ctrl = host->ctrl;
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- struct platform_device *pdev = host->pdev;
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+ struct device *dev = ctrl->dev;
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struct mtd_info *mtd;
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struct nand_chip *chip;
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int ret;
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@@ -2730,7 +2730,7 @@ static int brcmnand_init_cs(struct brcmn
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ret = of_property_read_u32(dn, "reg", &host->cs);
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if (ret) {
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- dev_err(&pdev->dev, "can't get chip-select\n");
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+ dev_err(dev, "can't get chip-select\n");
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return -ENXIO;
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}
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@@ -2739,13 +2739,13 @@ static int brcmnand_init_cs(struct brcmn
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nand_set_flash_node(chip, dn);
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nand_set_controller_data(chip, host);
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- mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
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+ mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d",
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host->cs);
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if (!mtd->name)
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return -ENOMEM;
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mtd->owner = THIS_MODULE;
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- mtd->dev.parent = &pdev->dev;
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+ mtd->dev.parent = dev;
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chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl;
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chip->legacy.cmdfunc = brcmnand_cmdfunc;
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@ -0,0 +1,63 @@
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From: Florian Fainelli <f.fainelli@gmail.com>
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Subject: [PATCH v3 4/9] mtd: rawnand: brcmnand: Move OF operations out of brcmnand_init_cs()
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Date: Fri, 07 Jan 2022 10:46:09 -0800
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Content-Type: text/plain; charset="utf-8"
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In order to initialize a given chip select object for use by the
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brcmnand driver, move all of the Device Tree specific routines outside
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of brcmnand_init_cs() in order to make it usable in a platform data
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configuration which will be necessary for supporting BCMA chips.
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No functional changes introduced.
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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drivers/mtd/nand/raw/brcmnand/brcmnand.c | 20 +++++++++++---------
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1 file changed, 11 insertions(+), 9 deletions(-)
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -2719,7 +2719,7 @@ static const struct nand_controller_ops
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.attach_chip = brcmnand_attach_chip,
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};
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-static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
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+static int brcmnand_init_cs(struct brcmnand_host *host)
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{
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struct brcmnand_controller *ctrl = host->ctrl;
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struct device *dev = ctrl->dev;
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@@ -2728,16 +2728,9 @@ static int brcmnand_init_cs(struct brcmn
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int ret;
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u16 cfg_offs;
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- ret = of_property_read_u32(dn, "reg", &host->cs);
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- if (ret) {
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- dev_err(dev, "can't get chip-select\n");
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- return -ENXIO;
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- }
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-
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mtd = nand_to_mtd(&host->chip);
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chip = &host->chip;
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- nand_set_flash_node(chip, dn);
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nand_set_controller_data(chip, host);
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mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d",
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host->cs);
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@@ -3144,7 +3137,16 @@ int brcmnand_probe(struct platform_devic
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host->pdev = pdev;
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host->ctrl = ctrl;
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- ret = brcmnand_init_cs(host, child);
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+ ret = of_property_read_u32(child, "reg", &host->cs);
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+ if (ret) {
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+ dev_err(dev, "can't get chip-select\n");
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+ devm_kfree(dev, host);
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+ continue;
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+ }
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+
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+ nand_set_flash_node(&host->chip, child);
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+
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+ ret = brcmnand_init_cs(host);
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if (ret) {
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devm_kfree(dev, host);
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continue; /* Try all chip-selects */
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@ -0,0 +1,91 @@
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From: Florian Fainelli <f.fainelli@gmail.com>
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Subject: [PATCH v3 5/9] mtd: rawnand: brcmnand: Allow working without interrupts
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Date: Fri, 07 Jan 2022 10:46:10 -0800
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Content-Type: text/plain; charset="utf-8"
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The BCMA devices include the brcmnand controller but they do not wire up
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any interrupt line, allow the main interrupt to be optional and update
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the completion path to also check for the lack of an interrupt line.
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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drivers/mtd/nand/raw/brcmnand/brcmnand.c | 52 +++++++++++-------------
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1 file changed, 24 insertions(+), 28 deletions(-)
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -216,7 +216,7 @@ struct brcmnand_controller {
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void __iomem *nand_base;
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void __iomem *nand_fc; /* flash cache */
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void __iomem *flash_dma_base;
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- unsigned int irq;
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+ int irq;
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unsigned int dma_irq;
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int nand_version;
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@@ -1590,7 +1590,7 @@ static bool brcmstb_nand_wait_for_comple
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bool err = false;
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int sts;
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- if (mtd->oops_panic_write) {
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+ if (mtd->oops_panic_write || ctrl->irq < 0) {
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/* switch to interrupt polling and PIO mode */
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disable_ctrl_irqs(ctrl);
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sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY,
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@@ -3095,33 +3095,29 @@ int brcmnand_probe(struct platform_devic
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}
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/* IRQ */
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- ctrl->irq = platform_get_irq(pdev, 0);
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- if ((int)ctrl->irq < 0) {
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- dev_err(dev, "no IRQ defined\n");
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- ret = -ENODEV;
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- goto err;
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- }
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-
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- /*
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- * Some SoCs integrate this controller (e.g., its interrupt bits) in
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- * interesting ways
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- */
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- if (soc) {
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- ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
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- DRV_NAME, ctrl);
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-
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- /* Enable interrupt */
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- ctrl->soc->ctlrdy_ack(ctrl->soc);
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- ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
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- } else {
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- /* Use standard interrupt infrastructure */
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- ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
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- DRV_NAME, ctrl);
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- }
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- if (ret < 0) {
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- dev_err(dev, "can't allocate IRQ %d: error %d\n",
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- ctrl->irq, ret);
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- goto err;
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+ ctrl->irq = platform_get_irq_optional(pdev, 0);
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+ if (ctrl->irq > 0) {
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+ /*
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+ * Some SoCs integrate this controller (e.g., its interrupt bits) in
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+ * interesting ways
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+ */
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+ if (soc) {
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+ ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
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+ DRV_NAME, ctrl);
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+
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+ /* Enable interrupt */
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+ ctrl->soc->ctlrdy_ack(ctrl->soc);
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+ ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
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+ } else {
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+ /* Use standard interrupt infrastructure */
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+ ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
|
||||
+ DRV_NAME, ctrl);
|
||||
+ }
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(dev, "can't allocate IRQ %d: error %d\n",
|
||||
+ ctrl->irq, ret);
|
||||
+ goto err;
|
||||
+ }
|
||||
}
|
||||
|
||||
for_each_available_child_of_node(dn, child) {
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
From: Florian Fainelli <f.fainelli@gmail.com>
|
||||
Subject: [PATCH v3 6/9] mtd: rawnand: brcmnand: Add platform data structure for BCMA
|
||||
Date: Fri, 07 Jan 2022 10:46:11 -0800
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
|
||||
Update the BCMA's chipcommon nand flash driver to detect which
|
||||
chip-select is used and pass that information via platform data to the
|
||||
brcmnand driver. Make sure that the brcmnand platform data structure is
|
||||
always at the beginning of the platform data of the "nflash" device
|
||||
created by BCMA to allow brcmnand to safely de-reference it.
|
||||
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
MAINTAINERS | 1 +
|
||||
drivers/bcma/driver_chipcommon_nflash.c | 20 +++++++++++++++++++-
|
||||
include/linux/bcma/bcma_driver_chipcommon.h | 5 +++++
|
||||
include/linux/platform_data/brcmnand.h | 12 ++++++++++++
|
||||
4 files changed, 37 insertions(+), 1 deletion(-)
|
||||
create mode 100644 include/linux/platform_data/brcmnand.h
|
||||
|
||||
--- a/MAINTAINERS
|
||||
+++ b/MAINTAINERS
|
||||
@@ -3712,6 +3712,7 @@ L: linux-mtd@lists.infradead.org
|
||||
L: bcm-kernel-feedback-list@broadcom.com
|
||||
S: Maintained
|
||||
F: drivers/mtd/nand/raw/brcmnand/
|
||||
+F: include/linux/platform_data/brcmnand.h
|
||||
|
||||
BROADCOM SYSTEMPORT ETHERNET DRIVER
|
||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||
--- a/drivers/bcma/driver_chipcommon_nflash.c
|
||||
+++ b/drivers/bcma/driver_chipcommon_nflash.c
|
||||
@@ -7,18 +7,28 @@
|
||||
|
||||
#include "bcma_private.h"
|
||||
|
||||
+#include <linux/bitops.h>
|
||||
#include <linux/platform_device.h>
|
||||
+#include <linux/platform_data/brcmnand.h>
|
||||
#include <linux/bcma/bcma.h>
|
||||
|
||||
+/* Alternate NAND controller driver name in order to allow both bcm47xxnflash
|
||||
+ * and bcma_brcmnand to be built into the same kernel image.
|
||||
+ */
|
||||
+static const char *bcma_nflash_alt_name = "bcma_brcmnand";
|
||||
+
|
||||
struct platform_device bcma_nflash_dev = {
|
||||
.name = "bcma_nflash",
|
||||
.num_resources = 0,
|
||||
};
|
||||
|
||||
+static const char *probes[] = { "bcm47xxpart", NULL };
|
||||
+
|
||||
/* Initialize NAND flash access */
|
||||
int bcma_nflash_init(struct bcma_drv_cc *cc)
|
||||
{
|
||||
struct bcma_bus *bus = cc->core->bus;
|
||||
+ u32 reg;
|
||||
|
||||
if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
|
||||
cc->core->id.rev != 38) {
|
||||
@@ -33,8 +43,16 @@ int bcma_nflash_init(struct bcma_drv_cc
|
||||
|
||||
cc->nflash.present = true;
|
||||
if (cc->core->id.rev == 38 &&
|
||||
- (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
|
||||
+ (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) {
|
||||
cc->nflash.boot = true;
|
||||
+ /* Determine the chip select that is being used */
|
||||
+ reg = bcma_cc_read32(cc, BCMA_CC_NAND_CS_NAND_SELECT) & 0xff;
|
||||
+ cc->nflash.brcmnand_info.chip_select = ffs(reg) - 1;
|
||||
+ cc->nflash.brcmnand_info.part_probe_types = probes;
|
||||
+ cc->nflash.brcmnand_info.ecc_stepsize = 512;
|
||||
+ cc->nflash.brcmnand_info.ecc_strength = 1;
|
||||
+ bcma_nflash_dev.name = bcma_nflash_alt_name;
|
||||
+ }
|
||||
|
||||
/* Prepare platform device, but don't register it yet. It's too early,
|
||||
* malloc (required by device_private_init) is not available yet. */
|
||||
--- a/include/linux/bcma/bcma_driver_chipcommon.h
|
||||
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
|
||||
@@ -3,6 +3,7 @@
|
||||
#define LINUX_BCMA_DRIVER_CC_H_
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
+#include <linux/platform_data/brcmnand.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
/** ChipCommon core registers. **/
|
||||
@@ -599,6 +600,10 @@ struct bcma_sflash {
|
||||
|
||||
#ifdef CONFIG_BCMA_NFLASH
|
||||
struct bcma_nflash {
|
||||
+ /* Must be the fist member for the brcmnand driver to
|
||||
+ * de-reference that structure.
|
||||
+ */
|
||||
+ struct brcmnand_platform_data brcmnand_info;
|
||||
bool present;
|
||||
bool boot; /* This is the flash the SoC boots from */
|
||||
};
|
||||
--- /dev/null
|
||||
+++ b/include/linux/platform_data/brcmnand.h
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+#ifndef BRCMNAND_PLAT_DATA_H
|
||||
+#define BRCMNAND_PLAT_DATA_H
|
||||
+
|
||||
+struct brcmnand_platform_data {
|
||||
+ int chip_select;
|
||||
+ const char * const *part_probe_types;
|
||||
+ unsigned int ecc_stepsize;
|
||||
+ unsigned int ecc_strength;
|
||||
+};
|
||||
+
|
||||
+#endif /* BRCMNAND_PLAT_DATA_H */
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
From: Florian Fainelli <f.fainelli@gmail.com>
|
||||
Subject: [PATCH v3 7/9] mtd: rawnand: brcmnand: Allow platform data instantation
|
||||
Date: Fri, 07 Jan 2022 10:46:12 -0800
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
|
||||
Make use of the recently refactored code in brcmnand_init_cs() and
|
||||
derive the chip-select from the platform data that is supplied. Update
|
||||
the various code paths to avoid relying on possibly non-existent
|
||||
resources, too.
|
||||
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 45 ++++++++++++++++++------
|
||||
1 file changed, 35 insertions(+), 10 deletions(-)
|
||||
|
||||
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
@@ -9,6 +9,7 @@
|
||||
#include <linux/delay.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
+#include <linux/platform_data/brcmnand.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/completion.h>
|
||||
#include <linux/interrupt.h>
|
||||
@@ -2719,7 +2720,8 @@ static const struct nand_controller_ops
|
||||
.attach_chip = brcmnand_attach_chip,
|
||||
};
|
||||
|
||||
-static int brcmnand_init_cs(struct brcmnand_host *host)
|
||||
+static int brcmnand_init_cs(struct brcmnand_host *host,
|
||||
+ const char * const *part_probe_types)
|
||||
{
|
||||
struct brcmnand_controller *ctrl = host->ctrl;
|
||||
struct device *dev = ctrl->dev;
|
||||
@@ -2772,7 +2774,7 @@ static int brcmnand_init_cs(struct brcmn
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
- ret = mtd_device_register(mtd, NULL, 0);
|
||||
+ ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
|
||||
if (ret)
|
||||
nand_cleanup(chip);
|
||||
|
||||
@@ -2941,17 +2943,15 @@ static int brcmnand_edu_setup(struct pla
|
||||
|
||||
int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
|
||||
{
|
||||
+ struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev);
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *dn = dev->of_node, *child;
|
||||
struct brcmnand_controller *ctrl;
|
||||
+ struct brcmnand_host *host;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
- /* We only support device-tree instantiation */
|
||||
- if (!dn)
|
||||
- return -ENODEV;
|
||||
-
|
||||
- if (!of_match_node(brcmnand_of_match, dn))
|
||||
+ if (dn && !of_match_node(brcmnand_of_match, dn))
|
||||
return -ENODEV;
|
||||
|
||||
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
|
||||
@@ -2978,7 +2978,7 @@ int brcmnand_probe(struct platform_devic
|
||||
/* NAND register range */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
ctrl->nand_base = devm_ioremap_resource(dev, res);
|
||||
- if (IS_ERR(ctrl->nand_base))
|
||||
+ if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc))
|
||||
return PTR_ERR(ctrl->nand_base);
|
||||
|
||||
/* Enable clock before using NAND registers */
|
||||
@@ -3122,7 +3122,6 @@ int brcmnand_probe(struct platform_devic
|
||||
|
||||
for_each_available_child_of_node(dn, child) {
|
||||
if (of_device_is_compatible(child, "brcm,nandcs")) {
|
||||
- struct brcmnand_host *host;
|
||||
|
||||
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
|
||||
if (!host) {
|
||||
@@ -3142,7 +3141,7 @@ int brcmnand_probe(struct platform_devic
|
||||
|
||||
nand_set_flash_node(&host->chip, child);
|
||||
|
||||
- ret = brcmnand_init_cs(host);
|
||||
+ ret = brcmnand_init_cs(host, NULL);
|
||||
if (ret) {
|
||||
devm_kfree(dev, host);
|
||||
continue; /* Try all chip-selects */
|
||||
@@ -3152,6 +3151,32 @@ int brcmnand_probe(struct platform_devic
|
||||
}
|
||||
}
|
||||
|
||||
+ if (!list_empty(&ctrl->host_list))
|
||||
+ return 0;
|
||||
+
|
||||
+ if (!pd) {
|
||||
+ ret = -ENODEV;
|
||||
+ goto err;
|
||||
+ }
|
||||
+
|
||||
+ /* If we got there we must have been probing via platform data */
|
||||
+ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
|
||||
+ if (!host) {
|
||||
+ ret = -ENOMEM;
|
||||
+ goto err;
|
||||
+ }
|
||||
+ host->pdev = pdev;
|
||||
+ host->ctrl = ctrl;
|
||||
+ host->cs = pd->chip_select;
|
||||
+ host->chip.ecc.size = pd->ecc_stepsize;
|
||||
+ host->chip.ecc.strength = pd->ecc_strength;
|
||||
+
|
||||
+ ret = brcmnand_init_cs(host, pd->part_probe_types);
|
||||
+ if (ret)
|
||||
+ goto err;
|
||||
+
|
||||
+ list_add_tail(&host->node, &ctrl->host_list);
|
||||
+
|
||||
/* No chip-selects could initialize properly */
|
||||
if (list_empty(&ctrl->host_list)) {
|
||||
ret = -ENODEV;
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
From: Florian Fainelli <f.fainelli@gmail.com>
|
||||
Subject: [PATCH v3 8/9] mtd: rawnand: brcmnand: BCMA controller uses command shift of 0
|
||||
Date: Fri, 07 Jan 2022 10:46:13 -0800
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
|
||||
For some odd and unexplained reason the BCMA NAND controller, albeit
|
||||
revision 3.4 uses a command shift of 0 instead of 24 as it should be,
|
||||
quirk that.
|
||||
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
@@ -913,6 +913,12 @@ static void brcmnand_wr_corr_thresh(stru
|
||||
|
||||
static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
|
||||
{
|
||||
+ /* Kludge for the BCMA-based NAND controller which does not actually
|
||||
+ * shift the command
|
||||
+ */
|
||||
+ if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl))
|
||||
+ return 0;
|
||||
+
|
||||
if (ctrl->nand_version < 0x0602)
|
||||
return 24;
|
||||
return 0;
|
||||
|
|
@ -0,0 +1,201 @@
|
|||
From: Florian Fainelli <f.fainelli@gmail.com>
|
||||
Subject: [PATCH v3 9/9] mtd: rawnand: brcmnand: Add BCMA shim
|
||||
Date: Fri, 07 Jan 2022 10:46:14 -0800
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
|
||||
Add a BCMA shim to allow us to register the brcmnand driver using the
|
||||
BCMA bus which provides indirect memory mapped access to SoC registers.
|
||||
|
||||
There are a number of registers that need to be byte swapped because
|
||||
they are natively big endian, coming directly from the NAND chip, and
|
||||
there is no bus interface unlike the iProc or STB platforms that
|
||||
performs the byte swapping for us.
|
||||
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
drivers/mtd/nand/raw/Kconfig | 13 +++
|
||||
drivers/mtd/nand/raw/brcmnand/Makefile | 2 +
|
||||
drivers/mtd/nand/raw/brcmnand/bcma_nand.c | 132 ++++++++++++++++++++++
|
||||
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 4 +
|
||||
4 files changed, 151 insertions(+)
|
||||
create mode 100644 drivers/mtd/nand/raw/brcmnand/bcma_nand.c
|
||||
|
||||
--- a/drivers/mtd/nand/raw/Kconfig
|
||||
+++ b/drivers/mtd/nand/raw/Kconfig
|
||||
@@ -236,6 +236,19 @@ config MTD_NAND_BRCMNAND
|
||||
originally designed for Set-Top Box but is used on various BCM7xxx,
|
||||
BCM3xxx, BCM63xxx, iProc/Cygnus and more.
|
||||
|
||||
+if MTD_NAND_BRCMNAND
|
||||
+
|
||||
+config MTD_NAND_BRCMNAND_BCMA
|
||||
+ tristate "Broadcom BCMA NAND controller"
|
||||
+ depends on BCMA_NFLASH
|
||||
+ depends on BCMA
|
||||
+ help
|
||||
+ Enables the BRCMNAND controller over BCMA on BCM47186/BCM5358 SoCs.
|
||||
+ The glue driver will take care of performing the low-level I/O
|
||||
+ operations to interface the BRCMNAND controller over the BCMA bus.
|
||||
+
|
||||
+endif # MTD_NAND_BRCMNAND
|
||||
+
|
||||
config MTD_NAND_BCM47XXNFLASH
|
||||
tristate "BCM4706 BCMA NAND controller"
|
||||
depends on BCMA_NFLASH
|
||||
--- a/drivers/mtd/nand/raw/brcmnand/Makefile
|
||||
+++ b/drivers/mtd/nand/raw/brcmnand/Makefile
|
||||
@@ -6,3 +6,5 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm6
|
||||
obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm6368_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmstb_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand.o
|
||||
+
|
||||
+obj-$(CONFIG_MTD_NAND_BRCMNAND_BCMA) += bcma_nand.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/mtd/nand/raw/brcmnand/bcma_nand.c
|
||||
@@ -0,0 +1,132 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-only
|
||||
+/*
|
||||
+ * Copyright © 2021 Broadcom
|
||||
+ */
|
||||
+#include <linux/bcma/bcma.h>
|
||||
+#include <linux/bcma/bcma_driver_chipcommon.h>
|
||||
+#include <linux/device.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+
|
||||
+#include "brcmnand.h"
|
||||
+
|
||||
+struct brcmnand_bcma_soc {
|
||||
+ struct brcmnand_soc soc;
|
||||
+ struct bcma_drv_cc *cc;
|
||||
+};
|
||||
+
|
||||
+static inline bool brcmnand_bcma_needs_swapping(u32 offset)
|
||||
+{
|
||||
+ switch (offset) {
|
||||
+ case BCMA_CC_NAND_SPARE_RD0:
|
||||
+ case BCMA_CC_NAND_SPARE_RD4:
|
||||
+ case BCMA_CC_NAND_SPARE_RD8:
|
||||
+ case BCMA_CC_NAND_SPARE_RD12:
|
||||
+ case BCMA_CC_NAND_SPARE_WR0:
|
||||
+ case BCMA_CC_NAND_SPARE_WR4:
|
||||
+ case BCMA_CC_NAND_SPARE_WR8:
|
||||
+ case BCMA_CC_NAND_SPARE_WR12:
|
||||
+ case BCMA_CC_NAND_DEVID:
|
||||
+ case BCMA_CC_NAND_DEVID_X:
|
||||
+ case BCMA_CC_NAND_SPARE_RD16:
|
||||
+ case BCMA_CC_NAND_SPARE_RD20:
|
||||
+ case BCMA_CC_NAND_SPARE_RD24:
|
||||
+ case BCMA_CC_NAND_SPARE_RD28:
|
||||
+ return true;
|
||||
+ }
|
||||
+
|
||||
+ return false;
|
||||
+}
|
||||
+
|
||||
+static inline struct brcmnand_bcma_soc *to_bcma_soc(struct brcmnand_soc *soc)
|
||||
+{
|
||||
+ return container_of(soc, struct brcmnand_bcma_soc, soc);
|
||||
+}
|
||||
+
|
||||
+static u32 brcmnand_bcma_read_reg(struct brcmnand_soc *soc, u32 offset)
|
||||
+{
|
||||
+ struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
|
||||
+ u32 val;
|
||||
+
|
||||
+ /* Offset into the NAND block and deal with the flash cache separately */
|
||||
+ if (offset == BRCMNAND_NON_MMIO_FC_ADDR)
|
||||
+ offset = BCMA_CC_NAND_CACHE_DATA;
|
||||
+ else
|
||||
+ offset += BCMA_CC_NAND_REVISION;
|
||||
+
|
||||
+ val = bcma_cc_read32(sc->cc, offset);
|
||||
+
|
||||
+ /* Swap if necessary */
|
||||
+ if (brcmnand_bcma_needs_swapping(offset))
|
||||
+ val = be32_to_cpu(val);
|
||||
+ return val;
|
||||
+}
|
||||
+
|
||||
+static void brcmnand_bcma_write_reg(struct brcmnand_soc *soc, u32 val,
|
||||
+ u32 offset)
|
||||
+{
|
||||
+ struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
|
||||
+
|
||||
+ /* Offset into the NAND block */
|
||||
+ if (offset == BRCMNAND_NON_MMIO_FC_ADDR)
|
||||
+ offset = BCMA_CC_NAND_CACHE_DATA;
|
||||
+ else
|
||||
+ offset += BCMA_CC_NAND_REVISION;
|
||||
+
|
||||
+ /* Swap if necessary */
|
||||
+ if (brcmnand_bcma_needs_swapping(offset))
|
||||
+ val = cpu_to_be32(val);
|
||||
+
|
||||
+ bcma_cc_write32(sc->cc, offset, val);
|
||||
+}
|
||||
+
|
||||
+static struct brcmnand_io_ops brcmnand_bcma_io_ops = {
|
||||
+ .read_reg = brcmnand_bcma_read_reg,
|
||||
+ .write_reg = brcmnand_bcma_write_reg,
|
||||
+};
|
||||
+
|
||||
+static void brcmnand_bcma_prepare_data_bus(struct brcmnand_soc *soc, bool prepare,
|
||||
+ bool is_param)
|
||||
+{
|
||||
+ struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
|
||||
+
|
||||
+ /* Reset the cache address to ensure we are already accessing the
|
||||
+ * beginning of a sub-page.
|
||||
+ */
|
||||
+ bcma_cc_write32(sc->cc, BCMA_CC_NAND_CACHE_ADDR, 0);
|
||||
+}
|
||||
+
|
||||
+static int brcmnand_bcma_nand_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev);
|
||||
+ struct brcmnand_bcma_soc *soc;
|
||||
+
|
||||
+ soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL);
|
||||
+ if (!soc)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ soc->cc = container_of(nflash, struct bcma_drv_cc, nflash);
|
||||
+ soc->soc.prepare_data_bus = brcmnand_bcma_prepare_data_bus;
|
||||
+ soc->soc.ops = &brcmnand_bcma_io_ops;
|
||||
+
|
||||
+ if (soc->cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
|
||||
+ dev_err(&pdev->dev, "Use bcm47xxnflash for 4706!\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ return brcmnand_probe(pdev, &soc->soc);
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver brcmnand_bcma_nand_driver = {
|
||||
+ .probe = brcmnand_bcma_nand_probe,
|
||||
+ .remove = brcmnand_remove,
|
||||
+ .driver = {
|
||||
+ .name = "bcma_brcmnand",
|
||||
+ .pm = &brcmnand_pm_ops,
|
||||
+ }
|
||||
+};
|
||||
+module_platform_driver(brcmnand_bcma_nand_driver);
|
||||
+
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_AUTHOR("Broadcom");
|
||||
+MODULE_DESCRIPTION("NAND controller driver glue for BCMA chips");
|
||||
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
@@ -595,7 +595,11 @@ enum {
|
||||
|
||||
static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)
|
||||
{
|
||||
+#if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA)
|
||||
return static_branch_unlikely(&brcmnand_soc_has_ops_key);
|
||||
+#else
|
||||
+ return false;
|
||||
+#endif
|
||||
}
|
||||
|
||||
static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
|
||||
Loading…
Reference in New Issue
Block a user