rockchip: remove Kernel 5.4
As v5.10 is the default kernel version now, the files for v5.4 can be dropped. Signed-off-by: David Bauer <mail@david-bauer.net>
This commit is contained in:
David Bauer
parent
13f326de3a
commit
e1780de5ce
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@ -1,628 +0,0 @@
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CONFIG_64BIT=y
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CONFIG_ARCH_CLOCKSOURCE_DATA=y
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MMAP_RND_BITS=18
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CONFIG_ARCH_MMAP_RND_BITS_MAX=33
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CONFIG_ARCH_MMAP_RND_BITS_MIN=18
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
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CONFIG_ARCH_PROC_KCORE_TEXT=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_SELECT_MEMORY_MODEL=y
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CONFIG_ARCH_SPARSEMEM_DEFAULT=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARC_EMAC_CORE=y
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CONFIG_ARM64=y
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CONFIG_ARM64_4K_PAGES=y
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CONFIG_ARM64_CNP=y
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CONFIG_ARM64_CONT_SHIFT=4
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CONFIG_ARM64_ERRATUM_819472=y
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CONFIG_ARM64_ERRATUM_824069=y
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CONFIG_ARM64_ERRATUM_826319=y
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CONFIG_ARM64_ERRATUM_827319=y
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CONFIG_ARM64_ERRATUM_832075=y
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CONFIG_ARM64_ERRATUM_843419=y
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CONFIG_ARM64_ERRATUM_845719=y
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CONFIG_ARM64_ERRATUM_858921=y
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CONFIG_ARM64_HW_AFDBM=y
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CONFIG_ARM64_LSE_ATOMICS=y
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CONFIG_ARM64_MODULE_PLTS=y
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CONFIG_ARM64_PAGE_SHIFT=12
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CONFIG_ARM64_PAN=y
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CONFIG_ARM64_PA_BITS=48
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CONFIG_ARM64_PA_BITS_48=y
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CONFIG_ARM64_PTR_AUTH=y
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CONFIG_ARM64_RAS_EXTN=y
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CONFIG_ARM64_SSBD=y
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CONFIG_ARM64_SVE=y
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# CONFIG_ARM64_SW_TTBR0_PAN is not set
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CONFIG_ARM64_TAGGED_ADDR_ABI=y
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CONFIG_ARM64_UAO=y
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CONFIG_ARM64_VA_BITS=48
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# CONFIG_ARM64_VA_BITS_39 is not set
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CONFIG_ARM64_VA_BITS_48=y
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CONFIG_ARM64_VHE=y
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CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
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# CONFIG_ARMV8_DEPRECATED is not set
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CONFIG_ARM_AMBA=y
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CONFIG_ARM_ARCH_TIMER=y
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CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
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CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
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CONFIG_ARM_CPUIDLE=y
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CONFIG_ARM_GIC=y
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CONFIG_ARM_GIC_V2M=y
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CONFIG_ARM_GIC_V3=y
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CONFIG_ARM_GIC_V3_ITS=y
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CONFIG_ARM_GIC_V3_ITS_PCI=y
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CONFIG_ARM_MHU=y
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CONFIG_ARM_PSCI_CPUIDLE=y
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CONFIG_ARM_PSCI_FW=y
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# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
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# CONFIG_ARM_SCMI_PROTOCOL is not set
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CONFIG_ARM_SCPI_CPUFREQ=y
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CONFIG_ARM_SCPI_POWER_DOMAIN=y
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CONFIG_ARM_SCPI_PROTOCOL=y
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CONFIG_ARM_SMMU=y
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CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
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CONFIG_ARM_SMMU_V3=y
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CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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CONFIG_BACKLIGHT_GPIO=y
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CONFIG_BACKLIGHT_PWM=y
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CONFIG_BLK_DEV_BSG=y
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CONFIG_BLK_DEV_BSGLIB=y
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# CONFIG_BLK_DEV_INITRD is not set
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CONFIG_BLK_DEV_INTEGRITY=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_NVME=y
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CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BLK_PM=y
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CONFIG_BLK_SCSI_REQUEST=y
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CONFIG_BLOCK_COMPAT=y
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CONFIG_BRCMSTB_GISB_ARB=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_BSD_PROCESS_ACCT_V3=y
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CONFIG_CHARGER_GPIO=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMA=y
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CONFIG_CMA_ALIGNMENT=8
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CONFIG_CMA_AREAS=7
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# CONFIG_CMA_DEBUG is not set
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# CONFIG_CMA_DEBUGFS is not set
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CONFIG_CMA_SIZE_MBYTES=5
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# CONFIG_CMA_SIZE_SEL_MAX is not set
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CONFIG_CMA_SIZE_SEL_MBYTES=y
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# CONFIG_CMA_SIZE_SEL_MIN is not set
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# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
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CONFIG_COMMON_CLK=y
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CONFIG_COMMON_CLK_RK808=y
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CONFIG_COMMON_CLK_SCPI=y
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CONFIG_COMPAT=y
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CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_COMPAT_BINFMT_ELF=y
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CONFIG_COMPAT_NETLINK_MESSAGES=y
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CONFIG_COMPAT_OLD_SIGACTION=y
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CONFIG_CONFIGFS_FS=y
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CONFIG_CONSOLE_TRANSLATIONS=y
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CONFIG_CONTIG_ALLOC=y
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CONFIG_CPUFREQ_DT=y
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CONFIG_CPUFREQ_DT_PLATDEV=y
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CONFIG_CPU_FREQ=y
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# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
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CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
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CONFIG_CPU_FREQ_GOV_ATTR_SET=y
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# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
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# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
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CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
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CONFIG_CPU_FREQ_GOV_POWERSAVE=y
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CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
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# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
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CONFIG_CPU_FREQ_STAT=y
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CONFIG_CPU_IDLE=y
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CONFIG_CPU_IDLE_GOV_MENU=y
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CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
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CONFIG_CPU_ISOLATION=y
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CONFIG_CPU_PM=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_THERMAL=y
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CONFIG_CRASH_CORE=y
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CONFIG_CRASH_DUMP=y
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CONFIG_CRC16=y
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# CONFIG_CRC32_SARWATE is not set
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CONFIG_CRC32_SLICEBY8=y
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CONFIG_CRC_T10DIF=y
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CONFIG_CROSS_MEMORY_ATTACH=y
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CONFIG_CRYPTO_AEAD=y
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CONFIG_CRYPTO_AEAD2=y
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CONFIG_CRYPTO_CRC32=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_CRCT10DIF=y
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# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
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CONFIG_CRYPTO_HASH=y
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CONFIG_CRYPTO_HASH2=y
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CONFIG_CRYPTO_MANAGER=y
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CONFIG_CRYPTO_MANAGER2=y
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CONFIG_CRYPTO_NULL2=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_BUGVERBOSE=y
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# CONFIG_DEVFREQ_GOV_PASSIVE is not set
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CONFIG_DEVFREQ_GOV_PERFORMANCE=y
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CONFIG_DEVFREQ_GOV_POWERSAVE=y
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CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
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CONFIG_DEVFREQ_GOV_USERSPACE=y
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# CONFIG_DEVFREQ_THERMAL is not set
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CONFIG_DEVMEM=y
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# CONFIG_DEVPORT is not set
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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CONFIG_DMADEVICES=y
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CONFIG_DMA_CMA=y
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CONFIG_DMA_DIRECT_REMAP=y
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CONFIG_DMA_ENGINE=y
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CONFIG_DMA_OF=y
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CONFIG_DMA_REMAP=y
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CONFIG_DMA_SHARED_BUFFER=y
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CONFIG_DNOTIFY=y
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CONFIG_DRM_RCAR_WRITEBACK=y
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# CONFIG_DRM_ROCKCHIP is not set
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CONFIG_DTC=y
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CONFIG_DT_IDLE_STATES=y
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CONFIG_DUMMY_CONSOLE=y
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CONFIG_DWMAC_DWC_QOS_ETH=y
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CONFIG_DWMAC_GENERIC=y
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CONFIG_DWMAC_ROCKCHIP=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_EEPROM_AT24=y
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CONFIG_EMAC_ROCKCHIP=y
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CONFIG_ENABLE_MUST_CHECK=y
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CONFIG_ENERGY_MODEL=y
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CONFIG_EXT4_FS=y
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CONFIG_EXT4_FS_POSIX_ACL=y
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CONFIG_EXTCON=y
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CONFIG_F2FS_FS=y
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CONFIG_FANOTIFY=y
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CONFIG_FHANDLE=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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# CONFIG_FLATMEM_MANUAL is not set
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# CONFIG_FORTIFY_SOURCE is not set
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CONFIG_FRAME_POINTER=y
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CONFIG_FRAME_WARN=2048
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CONFIG_FS_IOMAP=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FS_POSIX_ACL=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ARCH_TOPOLOGY=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_CPU_VULNERABILITIES=y
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CONFIG_GENERIC_CSUM=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
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CONFIG_GENERIC_GETTIMEOFDAY=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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CONFIG_GENERIC_IRQ_MIGRATION=y
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CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_PHY=y
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CONFIG_GENERIC_PINCONF=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_DWAPB=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_GENERIC_PLATFORM=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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# CONFIG_HARDENED_USERCOPY is not set
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CONFIG_HARDEN_BRANCH_PREDICTOR=y
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HID=y
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CONFIG_HID_GENERIC=y
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CONFIG_HOLES_IN_ZONE=y
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CONFIG_HOTPLUG_CPU=y
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CONFIG_HOTPLUG_PCI=y
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# CONFIG_HOTPLUG_PCI_CPCI is not set
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# CONFIG_HOTPLUG_PCI_PCIE is not set
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# CONFIG_HOTPLUG_PCI_SHPC is not set
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CONFIG_HUGETLBFS=y
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CONFIG_HUGETLB_PAGE=y
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CONFIG_HWMON=y
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CONFIG_HWSPINLOCK=y
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CONFIG_HW_CONSOLE=y
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_COMPAT=y
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CONFIG_I2C_HELPER_AUTO=y
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CONFIG_I2C_RK3X=y
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CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
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CONFIG_INDIRECT_PIO=y
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CONFIG_INPUT=y
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CONFIG_INPUT_EVDEV=y
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CONFIG_INPUT_FF_MEMLESS=y
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CONFIG_INPUT_KEYBOARD=y
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CONFIG_INPUT_LEDS=y
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CONFIG_INPUT_MATRIXKMAP=y
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# CONFIG_INPUT_MISC is not set
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# CONFIG_INPUT_RK805_PWRKEY is not set
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CONFIG_IOMMU_API=y
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# CONFIG_IOMMU_DEBUGFS is not set
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# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
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CONFIG_IOMMU_DMA=y
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CONFIG_IOMMU_IOVA=y
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CONFIG_IOMMU_IO_PGTABLE=y
|
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# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
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CONFIG_IOMMU_IO_PGTABLE_LPAE=y
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# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
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CONFIG_IOMMU_SUPPORT=y
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# CONFIG_IO_STRICT_DEVMEM is not set
|
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CONFIG_IO_URING=y
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_IRQ_FORCED_THREADING=y
|
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CONFIG_IRQ_MSI_IOMMU=y
|
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CONFIG_IRQ_TIME_ACCOUNTING=y
|
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CONFIG_IRQ_WORK=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KEXEC_CORE=y
|
||||
CONFIG_KEXEC_FILE=y
|
||||
# CONFIG_KEXEC_SIG is not set
|
||||
CONFIG_KSM=y
|
||||
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PWM=y
|
||||
CONFIG_LEDS_SYSCON=y
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
||||
CONFIG_LEDS_TRIGGER_PANIC=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=16
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LOG_BUF_SHIFT=19
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MAGIC_SYSRQ_SERIAL=y
|
||||
CONFIG_MAILBOX=y
|
||||
# CONFIG_MAILBOX_TEST is not set
|
||||
CONFIG_MANDATORY_FILE_LOCKING=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_BUS_MUX=y
|
||||
CONFIG_MDIO_BUS_MUX_GPIO=y
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_CORE=y
|
||||
CONFIG_MFD_RK808=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_CQHCI=y
|
||||
CONFIG_MMC_DW=y
|
||||
# CONFIG_MMC_DW_BLUEFIELD is not set
|
||||
# CONFIG_MMC_DW_EXYNOS is not set
|
||||
# CONFIG_MMC_DW_HI3798CV200 is not set
|
||||
# CONFIG_MMC_DW_K3 is not set
|
||||
# CONFIG_MMC_DW_PCI is not set
|
||||
CONFIG_MMC_DW_PLTFM=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MQ_IOSCHED_DEADLINE=y
|
||||
# CONFIG_MTD_CFI is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=256
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_NVME_CORE=y
|
||||
# CONFIG_NVME_MULTIPATH is not set
|
||||
# CONFIG_NVME_TCP is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IOMMU=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_POOL=y
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
# CONFIG_PCIEASPM_DEBUG is not set
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCIE_ROCKCHIP=y
|
||||
CONFIG_PCIE_ROCKCHIP_HOST=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PCI_STUB=y
|
||||
CONFIG_PGTABLE_LEVELS=4
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_ROCKCHIP_DP=y
|
||||
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_PCIE=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PHY_ROCKCHIP_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_RK805 is not set
|
||||
CONFIG_PINCTRL_ROCKCHIP=y
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
# CONFIG_PM_DEVFREQ_EVENT is not set
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POWER_AVS=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_SUPPLY_HWMON=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_PREEMPTION=y
|
||||
CONFIG_PREEMPT_COUNT=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
CONFIG_PREEMPT_RCU=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_PRINT_QUOTA_WARNING is not set
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_PROC_VMCORE=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_QFMT_V1 is not set
|
||||
# CONFIG_QFMT_V2 is not set
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QUOTACTL=y
|
||||
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
|
||||
CONFIG_RAID_ATTRS=y
|
||||
CONFIG_RANDOMIZE_BASE=y
|
||||
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_RAVE_SP_CORE is not set
|
||||
CONFIG_RCU_TRACE=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REFCOUNT_FULL=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_IRQ=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK808=y
|
||||
CONFIG_RELOCATABLE=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_ROCKCHIP_GRF=y
|
||||
CONFIG_ROCKCHIP_IODOMAIN=y
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_ROCKCHIP_MBOX=y
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
# CONFIG_ROCKCHIP_SARADC is not set
|
||||
CONFIG_ROCKCHIP_THERMAL=y
|
||||
CONFIG_ROCKCHIP_TIMER=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RSEQ=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_RK808=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_NVMEM=y
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCSI=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_SCSI_SAS_ATTRS=y
|
||||
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||
CONFIG_SCSI_SAS_LIBSAS=y
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_EXAR=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SIMPLE_PM_BUS=y
|
||||
CONFIG_SLUB_DEBUG=y
|
||||
CONFIG_SMP=y
|
||||
# CONFIG_SND_SOC_ROCKCHIP is not set
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_MANUAL=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_DYNAMIC=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_ROCKCHIP=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
# CONFIG_SQUASHFS_EMBEDDED is not set
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_STMMAC_PLATFORM=y
|
||||
# CONFIG_STMMAC_SELFTESTS is not set
|
||||
CONFIG_STRICT_DEVMEM=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
CONFIG_SYSVIPC_COMPAT=y
|
||||
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
|
||||
# CONFIG_TEXTSEARCH is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
|
||||
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
|
||||
CONFIG_TRANSPARENT_HUGE_PAGECACHE=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_TYPEC=y
|
||||
# CONFIG_TYPEC_DP_ALTMODE is not set
|
||||
CONFIG_TYPEC_FUSB302=y
|
||||
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
|
||||
# CONFIG_TYPEC_TCPCI is not set
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
# CONFIG_TYPEC_TPS6598X is not set
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# CONFIG_UEVENT_HELPER is not set
|
||||
CONFIG_UNINLINE_SPIN_UNLOCK=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_HOST=y
|
||||
CONFIG_USB_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||
CONFIG_USB_HID=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_ROLE_SWITCH=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
# CONFIG_WATCHDOG is not set
|
||||
CONFIG_XARRAY_MULTI=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
|
|
@ -1,404 +0,0 @@
|
|||
From 0720be5371c806c1b89936984a321248fa739bea Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Fri, 10 Jul 2020 15:57:46 +0200
|
||||
Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S
|
||||
|
||||
This adds support for the NanoPi R2S from FriendlyARM.
|
||||
|
||||
Rockchip RK3328 SoC
|
||||
1GB DDR4 RAM
|
||||
Gigabit Ethernet (WAN)
|
||||
Gigabit Ethernet (USB3) (LAN)
|
||||
USB 2.0 Host Port
|
||||
MicroSD slot
|
||||
Reset button
|
||||
WAN - LAN - SYS LED
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 368 ++++++++++++++++++
|
||||
2 files changed, 369 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -1,6 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -0,0 +1,368 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include "rk3328.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R2S";
|
||||
+ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ gmac_clk: gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "gmac_clk";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ reset {
|
||||
+ label = "reset";
|
||||
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ debounce-interval = <50>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ lan_led: led-0 {
|
||||
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "nanopi-r2s:green:lan";
|
||||
+ };
|
||||
+
|
||||
+ sys_led: led-1 {
|
||||
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "nanopi-r2s:red:sys";
|
||||
+ };
|
||||
+
|
||||
+ wan_led: led-2 {
|
||||
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "nanopi-r2s:green:wan";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_io_sdio: sdmmcio-regulator {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-0 = <&sdio_vcc_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vcc_io_sdio";
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-settling-time-us = <5000>;
|
||||
+ regulator-type = "voltage";
|
||||
+ startup-delay-us = <2000>;
|
||||
+ states = <1800000 0x1
|
||||
+ 3300000 0x0>;
|
||||
+ vin-supply = <&vcc_io_33>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sd: sdmmc-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-0 = <&sdmmc0m1_gpio>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vcc_sd";
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc_io_33>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_5v: vdd-5v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vdd_5v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
|
||||
+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-handle = <&rtl8211e>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ phy-supply = <&vcc_io_33>;
|
||||
+ pinctrl-0 = <&rgmiim1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ rx_delay = <0x18>;
|
||||
+ snps,aal;
|
||||
+ tx_delay = <0x24>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ rtl8211e: ethernet-phy@1 {
|
||||
+ reg = <1>;
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk805: pmic@18 {
|
||||
+ compatible = "rockchip,rk805";
|
||||
+ reg = <0x18>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "xin32k", "rk805-clkout2";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ pinctrl-names = "default";
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vdd_5v>;
|
||||
+ vcc2-supply = <&vdd_5v>;
|
||||
+ vcc3-supply = <&vdd_5v>;
|
||||
+ vcc4-supply = <&vdd_5v>;
|
||||
+ vcc5-supply = <&vcc_io_33>;
|
||||
+ vcc6-supply = <&vdd_5v>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_log: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_arm: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_arm";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <950000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_io_33: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_io_33";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_18: LDO_REG1 {
|
||||
+ regulator-name = "vcc_18";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc18_emmc: LDO_REG2 {
|
||||
+ regulator-name = "vcc18_emmc";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_10: LDO_REG3 {
|
||||
+ regulator-name = "vdd_10";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1000000>;
|
||||
+ regulator-max-microvolt = <1000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ pmuio-supply = <&vcc_io_33>;
|
||||
+ vccio1-supply = <&vcc_io_33>;
|
||||
+ vccio2-supply = <&vcc18_emmc>;
|
||||
+ vccio3-supply = <&vcc_io_sdio>;
|
||||
+ vccio4-supply = <&vcc_18>;
|
||||
+ vccio5-supply = <&vcc_io_33>;
|
||||
+ vccio6-supply = <&vcc_io_33>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ button {
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethernet-phy {
|
||||
+ eth_phy_reset_pin: eth-phy-reset-pin {
|
||||
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ lan_led_pin: lan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ sys_led_pin: sys-led-pin {
|
||||
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sd {
|
||||
+ sdio_vcc_pin: sdio-vcc-pin {
|
||||
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
|
||||
+ pinctrl-names = "default";
|
||||
+ sd-uhs-sdr12;
|
||||
+ sd-uhs-sdr25;
|
||||
+ sd-uhs-sdr50;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc_sd>;
|
||||
+ vqmmc-supply = <&vcc_io_sdio>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <0>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb20_otg {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
From 8a469ee35606ba65448d54e5a2a23302f7e79e3c Mon Sep 17 00:00:00 2001
|
||||
From: Carlos de Paula <me@carlosedp.com>
|
||||
Date: Tue, 18 Feb 2020 17:10:37 -0500
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add txpbl node for RK3399/RK3328
|
||||
|
||||
Some rockchip SoCs like the RK3399 and RK3328 exhibit an issue
|
||||
where tx checksumming does not work with packets larger than 1498.
|
||||
|
||||
The default Programmable Buffer Length for TX in these GMAC's is
|
||||
not suitable for MTUs higher than 1498. The workaround is to disable
|
||||
TX offloading with 'ethtool -K eth0 tx off rx off' causing performance
|
||||
impacts as it disables hardware checksumming.
|
||||
|
||||
This patch sets snps,txpbl to 0x4 which is a safe number tested ok for
|
||||
the most popular MTU value of 1500.
|
||||
|
||||
For reference, see https://lkml.org/lkml/2019/4/1/1382.
|
||||
|
||||
Signed-off-by: Carlos de Paula <me@carlosedp.com>
|
||||
Link: https://lore.kernel.org/r/20200218221040.10955-1-me@carlosedp.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 ++
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
|
||||
2 files changed, 3 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -857,6 +857,7 @@
|
||||
resets = <&cru SRST_GMAC2IO_A>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
+ snps,txpbl = <0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -878,6 +879,7 @@
|
||||
reset-names = "stmmaceth", "mac-phy";
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&phy>;
|
||||
+ snps,txpbl = <0x4>;
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -291,6 +291,7 @@
|
||||
resets = <&cru SRST_A_GMAC>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
+ snps,txpbl = <0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
From bc6c96d850419e71dbc9b0094ccc9b668ba9be43 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Mon, 28 Sep 2020 22:54:52 +0200
|
||||
Subject: [PATCH] rockchip: rk3328: add compatible to NanoPi R2S ethernet PHY
|
||||
|
||||
This adds the compatible property to the NanoPi R2S ethernet PHY node.
|
||||
Otherwise, the PHY might not be probed, as the PHY ID reads all 0xff
|
||||
when it is still in reset.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -134,6 +134,8 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
rtl8211e: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-id001c.c915",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
pinctrl-0 = <ð_phy_reset_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
From f2962ed3805c5b74948d00e4e6fbb33388261ba8 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Sun, 4 Oct 2020 16:43:29 +0200
|
||||
Subject: [PATCH] rockchip: rk3328: fix NanoPi R2S GMAC clock name
|
||||
|
||||
This commit fixes the name for the GMAC clock to gmac_clkin, as this is
|
||||
the name of the clock provided by the rk3328-clk driver.
|
||||
|
||||
Without this commit, the GMAC will not work in TX direction.
|
||||
|
||||
Suggested-by: Tobias Waldvogel <tobias.waldvogel@gmail.com>
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -20,7 +20,7 @@
|
||||
gmac_clk: gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
- clock-output-names = "gmac_clk";
|
||||
+ clock-output-names = "gmac_clkin";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
|
|
@ -1,177 +0,0 @@
|
|||
From db792e9adbf85ffc9d6b0b060ac3c8e3148c8992 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Fri, 19 Mar 2021 13:16:27 +0800
|
||||
Subject: [PATCH] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S
|
||||
|
||||
This adds support for the NanoPi R4S from FriendlyArm.
|
||||
|
||||
Rockchip RK3399 SoC
|
||||
1GB DDR3 or 4GB LPDDR4 RAM
|
||||
Gigabit Ethernet (WAN)
|
||||
Gigabit Ethernet (PCIe) (LAN)
|
||||
USB 3.0 Port x 2
|
||||
MicroSD slot
|
||||
Reset button
|
||||
WAN - LAN - SYS LED
|
||||
|
||||
Co-developed-by: Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
[minor adjustments]
|
||||
Co-developed-by: Marty Jones <mj8263788@gmail.com>
|
||||
Signed-off-by: Marty Jones <mj8263788@gmail.com>
|
||||
[further adjustments, fixed format issues]
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210319051627.814-2-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 133 +++++++++++++++++++++
|
||||
2 files changed, 134 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-le
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -0,0 +1,133 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * FriendlyElec NanoPC-T4 board device tree source
|
||||
+ *
|
||||
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2018 Collabora Ltd.
|
||||
+ *
|
||||
+ * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
+ * Copyright (c) 2020 Marty Jones <mj8263788@gmail.com>
|
||||
+ * Copyright (c) 2021 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3399-nanopi4.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R4S";
|
||||
+ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
|
||||
+
|
||||
+ /delete-node/ display-subsystem;
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
|
||||
+
|
||||
+ /delete-node/ status;
|
||||
+
|
||||
+ lan_led: led-lan {
|
||||
+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:lan";
|
||||
+ };
|
||||
+
|
||||
+ sys_led: led-sys {
|
||||
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "red:sys";
|
||||
+ default-state = "on";
|
||||
+ };
|
||||
+
|
||||
+ wan_led: led-wan {
|
||||
+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:wan";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+
|
||||
+ /delete-node/ power;
|
||||
+
|
||||
+ reset {
|
||||
+ debounce-interval = <50>;
|
||||
+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
|
||||
+ label = "reset";
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_5v: vdd-5v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vdd_5v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&emmc_phy {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&i2c4 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&pcie0 {
|
||||
+ max-link-speed = <1>;
|
||||
+ num-lanes = <1>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gpio-leds {
|
||||
+ /delete-node/ leds-gpio;
|
||||
+
|
||||
+ lan_led_pin: lan-led-pin {
|
||||
+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ sys_led_pin: sys-led-pin {
|
||||
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rockchip-key {
|
||||
+ /delete-node/ power-key;
|
||||
+
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&sdio0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_host {
|
||||
+ phy-supply = <&vdd_5v>;
|
||||
+};
|
||||
+
|
||||
+&u2phy1_host {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_0 {
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&vcc3v3_sys {
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+};
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Mon, 7 Jun 2021 15:45:37 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
|
||||
|
||||
NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which
|
||||
stores the MAC address.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -68,6 +68,15 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+&i2c2 {
|
||||
+ eeprom@51 {
|
||||
+ compatible = "microchip,24c02", "atmel,24c02";
|
||||
+ reg = <0x51>;
|
||||
+ pagesize = <16>;
|
||||
+ read-only; /* This holds our MAC */
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&i2c4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Fri, 10 Jul 2020 21:38:20 +0200
|
||||
Subject: [PATCH] rockchip: use system LED for OpenWrt
|
||||
|
||||
Use the SYS LED on the casing for showing system status.
|
||||
|
||||
This patch is kept separate from the NanoPi R2S support patch, as i plan
|
||||
on submitting the device support upstream.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
|
||||
1 file changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -13,6 +13,13 @@
|
||||
model = "FriendlyElec NanoPi R2S";
|
||||
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
|
||||
|
||||
+ aliases {
|
||||
+ led-boot = &sys_led;
|
||||
+ led-failsafe = &sys_led;
|
||||
+ led-running = &sys_led;
|
||||
+ led-upgrade = &sys_led;
|
||||
+ };
|
||||
+
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
From: William Wu <william.wu@rock-chips.com>
|
||||
|
||||
RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
|
||||
core's general architecture. It can act as static xHCI host
|
||||
controller, static device controller, USB 3.0/2.0 OTG basing
|
||||
on ID of USB3.0 PHY.
|
||||
|
||||
Signed-off-by: William Wu <william.wu@rock-chips.com>
|
||||
Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
|
||||
|
||||
---
|
||||
|
||||
NOTE: This binding still has issues. From the original thread:
|
||||
|
||||
the rk3328 usb3-phy has an issue with detecting any plugin events
|
||||
after a previous device got removed - see the inno-usb3-phy driver
|
||||
in the vendor kernel.
|
||||
|
||||
The current state is good-enough for enabling the USB3 attached LAN
|
||||
port of the NanoPi R2S. However, it might explode depending on your
|
||||
use-case. You've been warned.
|
||||
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
|
||||
1 file changed, 27 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -938,6 +938,33 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ usbdrd3: usb@ff600000 {
|
||||
+ compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
|
||||
+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
|
||||
+ <&cru ACLK_USB3OTG>;
|
||||
+ clock-names = "ref_clk", "suspend_clk",
|
||||
+ "bus_clk";
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ ranges;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ usbdrd_dwc3: dwc3@ff600000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x0 0xff600000 0x0 0x100000>;
|
||||
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ dr_mode = "otg";
|
||||
+ phy_type = "utmi_wide";
|
||||
+ snps,dis_enblslpm_quirk;
|
||||
+ snps,dis-u2-freeclk-exists-quirk;
|
||||
+ snps,dis_u2_susphy_quirk;
|
||||
+ snps,dis_u3_susphy_quirk;
|
||||
+ snps,dis-del-phy-power-chg-quirk;
|
||||
+ snps,dis-tx-ipgap-linecheck-quirk;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
gic: interrupt-controller@ff811000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
From 0fc3b9b7619c4878f73a6a7989863f0d1a3fd392 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Fri, 10 Jul 2020 21:12:16 +0200
|
||||
Subject: [PATCH] rockchip: enabled LAN port on NanoPi R2S
|
||||
|
||||
Enable the USB3 port on the FriendlyARM NanoPi R2S.
|
||||
This is required for the USB3 attached LAN port to work.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 27 +++++++++++++++++++
|
||||
1 file changed, 27 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -44,6 +44,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ vcc_rtl8153: vcc-rtl8153-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rtl8153_en_drv>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-name = "vcc_rtl8153";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ enable-active-high;
|
||||
+ };
|
||||
+
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
|
||||
@@ -269,6 +281,12 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ usb {
|
||||
+ rtl8153_en_drv: rtl8153-en-drv {
|
||||
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
@@ -375,3 +393,12 @@
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+&usbdrd3 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3 {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Sun, 26 Jul 2020 13:32:59 +0200
|
||||
Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
|
||||
|
||||
This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
|
||||
NanoPi R2S. Add the correct value for the RTL8153 LED configuration
|
||||
register to match the blink behavior of the other port on the device.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -401,4 +401,11 @@
|
||||
&usbdrd_dwc3 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
+
|
||||
+ usb-eth@2 {
|
||||
+ compatible = "realtek,rtl8153";
|
||||
+ reg = <2>;
|
||||
+
|
||||
+ realtek,led-data = <0x87>;
|
||||
+ };
|
||||
};
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
From e12f67fe83446432ef16704c22ec23bd1dbcd094 Mon Sep 17 00:00:00 2001
|
||||
From: Vicente Bergas <vicencb@gmail.com>
|
||||
Date: Tue, 1 Dec 2020 16:41:32 +0100
|
||||
Subject: arm64: dts: rockchip: use USB host by default on rk3399-rock-pi-4
|
||||
|
||||
Based on the board schematics at
|
||||
https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf
|
||||
on page 19 there is an USB Type-A receptacle being used as an USB-OTG port.
|
||||
|
||||
But the Type-A connector is not valid for OTG operation, for this reason
|
||||
there is a switch to select host or device role.
|
||||
This is non-compliant and error prone because switching is manual.
|
||||
So, use host mode as it corresponds for a Type-A receptacle.
|
||||
|
||||
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
|
||||
@@ -684,7 +684,7 @@
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
status = "okay";
|
||||
- dr_mode = "otg";
|
||||
+ dr_mode = "host";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
Loading…
Reference in New Issue
Block a user