ipq806x: add support for Arris TR4400 v2 / RAC2V1A
Hardware specs:
SoC: Qualcomm IPQ8065 (dual core Cortex-A15)
RAM: 512 MB DDR3
Flash: 256 MB NAND, 32 MB NOR
WiFi: QCA9983 2.4 GHz, QCA9984 5 GHz
Switch: QCA8337
Ethernet: 5x 10/100/1000 Mbit/s
USB: 1x USB 3.0 Type-A
Buttons: WPS, Reset
Power: 12 VDC, 2.5 A
Ethernet ports:
1x WAN: connected to eth2
4x LAN: connected via the switch to eth0 and eth1
(eth0 is disabled in OEM firmware)
MAC addresses (OEM and OpenWrt):
fw_env @ 0x00 d4🆎82:??:??:?a LAN (eth1)
fw_env @ 0x06 d4🆎82:??:??:?b WAN (eth2)
fw_env @ 0x0c d4🆎82:??:??:?c WLAN 2.4 GHz (ath1)
fw_env @ 0x12 d4🆎82:??:??:?d WLAN 5 GHz (ath0)
fw_env @ 0x18 d4🆎82:??:??:?e OEM usage unknown (eth0 in OpenWrt)
OID d4🆎82 is registered to:
ARRIS Group, Inc., 6450 Sequence Drive, San Diego CA 92121, US
More info:
https://openwrt.org/inbox/toh/arris/tr4400_v2
IMPORTANT:
This port requires moving the 'fw_env' partition prior to first boot to
consolidate 70% of the usable space in flash into a contiguous partition.
'fw_env' contains factory-programmed MAC addresses, SSIDs, and passwords.
Its contents must be copied to 'rootfs_1' prior to booting via initramfs.
Note that the stock 'fw_env' partition will be wiped during sysupgrade.
A writable 'stock_fw_env' partition pointing to the old, stock location
is included in the port to help rolling back this change if desired.
Installation:
- Requires serial access and a TFTP server.
- Fully boot stock, press ENTER, type in:
mtd erase /dev/mtd21
dd if=/dev/mtd22 bs=128K count=1 | mtd write - /dev/mtd21
umount /config && ubidetach -m 23 && mtd erase /dev/mtd23
- Reboot and interrupt U-Boot by pressing a key, type in:
set mtdids 'nand0=nand0'
set mtdparts 'mtdparts=nand0:155M@0x6500000(mtd_ubi)'
set bootcmd 'ubi part mtd_ubi && ubi read 0x44000000 kernel && bootm'
env save
- Setup TFTP server serving initramfs image as 'recovery.bin', type in:
set ipaddr 192.168.1.1
set serverip 192.168.1.2
tftpboot recovery.bin && bootm
- Use sysupgrade to install squashfs image.
This port is based on work done by AmadeusGhost <amadeus@jmu.edu.cn>.
Signed-off-by: Rodrigo Balerdi <lanchon@gmail.com>
[add 5.15 changes for 0069-arm-boot-add-dts-files.patch]
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
This commit is contained in:
Rodrigo Balerdi
Sungbo Eo
parent
f4e219fd5e
commit
f8b0010dfb
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@ -30,6 +30,7 @@ ubootenv_mtdinfo () {
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}
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case "$board" in
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arris,tr4400-v2|\
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askey,rt4230w-rev6)
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ubootenv_add_uci_config "/dev/mtd9" "0x0" "0x40000" "0x20000"
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;;
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@ -11,6 +11,11 @@ board_config_update
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board=$(board_name)
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case "$board" in
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arris,tr4400-v2)
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ucidef_set_interfaces_lan_wan "eth1" "eth2"
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ucidef_add_switch "switch0" \
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"1:lan" "2:lan" "3:lan" "4:lan" "6u@eth1" "0u@eth0"
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;;
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askey,rt4230w-rev6 |\
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asrock,g10 |\
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nec,wg2600hp)
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@ -10,6 +10,7 @@ platform_check_image() {
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platform_do_upgrade() {
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case "$(board_name)" in
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arris,tr4400-v2 |\
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askey,rt4230w-rev6 |\
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compex,wpq864|\
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netgear,d7800 |\
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@ -0,0 +1,425 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "qcom-ipq8065.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Arris TR4400 v2";
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compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
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memory@0 {
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reg = <0x42000000 0x1e000000>;
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device_type = "memory";
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};
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aliases {
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led-boot = &led_status_blue;
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led-failsafe = &led_status_red;
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led-running = &led_status_blue;
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led-upgrade = &led_status_red;
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};
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chosen {
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bootargs = "rootfstype=squashfs noinitrd";
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};
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keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&button_pins>;
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pinctrl-names = "default";
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reset {
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label = "reset";
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gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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debounce-interval = <60>;
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wakeup-source;
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};
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wps {
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label = "wps";
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gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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debounce-interval = <60>;
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wakeup-source;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&led_pins>;
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pinctrl-names = "default";
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led_status_red: status_red {
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label = "red:status";
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gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
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};
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led_status_blue: status_blue {
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label = "blue:status";
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gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&qcom_pinmux {
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button_pins: button_pins {
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mux {
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pins = "gpio6", "gpio54";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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led_pins: led_pins {
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mux {
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pins = "gpio7", "gpio8";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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rgmii2_pins: rgmii2_pins {
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tx {
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pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
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input-disable;
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};
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};
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spi_pins: spi_pins {
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cs {
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pins = "gpio20";
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drive-strength = <12>;
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};
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};
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};
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&gsbi5 {
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qcom,mode = <GSBI_PROT_SPI>;
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status = "okay";
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spi@1a280000 {
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status = "okay";
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pinctrl-0 = <&spi_pins>;
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pinctrl-names = "default";
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cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
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flash@0 {
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compatible = "everspin,mr25h256";
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spi-max-frequency = <40000000>;
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reg = <0>;
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};
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};
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};
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&nand {
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status = "okay";
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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nand@0 {
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reg = <0>;
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compatible = "qcom,nandcs";
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nand-ecc-strength = <4>;
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nand-bus-width = <8>;
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nand-ecc-step-size = <512>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "0:SBL1";
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reg = <0x0000000 0x0040000>;
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read-only;
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};
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partition@40000 {
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label = "0:MIBIB";
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reg = <0x0040000 0x0140000>;
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read-only;
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};
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partition@180000 {
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label = "0:SBL2";
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reg = <0x0180000 0x0140000>;
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read-only;
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};
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partition@2c0000 {
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label = "0:SBL3";
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reg = <0x02c0000 0x0280000>;
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read-only;
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};
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partition@540000 {
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label = "0:DDRCONFIG";
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reg = <0x0540000 0x0120000>;
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read-only;
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};
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partition@660000 {
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label = "0:SSD";
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reg = <0x0660000 0x0120000>;
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read-only;
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};
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partition@780000 {
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label = "0:TZ";
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reg = <0x0780000 0x0280000>;
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read-only;
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};
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partition@a00000 {
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label = "0:RPM";
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reg = <0x0a00000 0x0280000>;
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read-only;
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};
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partition@c80000 {
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label = "0:APPSBL";
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reg = <0x0c80000 0x0500000>;
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read-only;
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};
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partition@1180000 {
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label = "0:APPSBLENV";
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reg = <0x1180000 0x0080000>;
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};
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partition@1200000 {
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label = "0:ART";
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reg = <0x1200000 0x0140000>;
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read-only;
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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precal_ART_1000: precal@1000 {
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reg = <0x1000 0x2f20>;
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};
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precal_ART_5000: precal@5000 {
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reg = <0x5000 0x2f20>;
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};
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};
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stock_partition@1340000 {
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label = "stock_rootfs";
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reg = <0x1340000 0x4000000>;
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};
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partition@5340000 {
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label = "0:BOOTCONFIG";
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reg = <0x5340000 0x0060000>;
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read-only;
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};
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partition@53a0000 {
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label = "0:SBL2_1";
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reg = <0x53a0000 0x0140000>;
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read-only;
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};
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partition@54e0000 {
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label = "0:SBL3_1";
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reg = <0x54e0000 0x0280000>;
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read-only;
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};
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partition@5760000 {
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label = "0:DDRCONFIG_1";
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reg = <0x5760000 0x0120000>;
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read-only;
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};
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partition@5880000 {
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label = "0:SSD_1";
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reg = <0x5880000 0x0120000>;
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read-only;
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};
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partition@59a0000 {
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label = "0:TZ_1";
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reg = <0x59a0000 0x0280000>;
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read-only;
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};
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partition@5c20000 {
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label = "0:RPM_1";
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reg = <0x5c20000 0x0280000>;
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read-only;
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};
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partition@5ea0000 {
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label = "0:BOOTCONFIG1";
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reg = <0x5ea0000 0x0060000>;
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read-only;
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};
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partition@5f00000 {
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label = "0:APPSBL_1";
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reg = <0x5f00000 0x0500000>;
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read-only;
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};
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stock_partition@6400000 {
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label = "stock_rootfs_1";
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reg = <0x6400000 0x4000000>;
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};
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stock_partition@a400000 {
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label = "stock_fw_env";
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reg = <0xa400000 0x0100000>;
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};
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stock_partition@a500000 {
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label = "stock_config";
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reg = <0xa500000 0x0800000>;
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};
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stock_partition@ad00000 {
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label = "stock_PKI";
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reg = <0xad00000 0x0200000>;
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};
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stock_partition@af00000 {
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label = "stock_scfgmgr";
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reg = <0xaf00000 0x0100000>;
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};
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partition@6400000 {
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label = "fw_env";
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reg = <0x6400000 0x0100000>;
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_fw_env_0: macaddr@0 {
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reg = <0x00 0x6>;
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};
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macaddr_fw_env_6: macaddr@6 {
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reg = <0x06 0x6>;
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};
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macaddr_fw_env_c: macaddr@c {
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reg = <0x0c 0x6>;
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};
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macaddr_fw_env_12: macaddr@12 {
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reg = <0x12 0x6>;
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};
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macaddr_fw_env_18: macaddr@18 {
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reg = <0x18 0x6>;
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};
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};
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partition@6500000 {
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label = "ubi";
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reg = <0x6500000 0x9b00000>;
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};
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partition@1340000 {
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label = "extra";
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reg = <0x1340000 0x4000000>;
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};
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};
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};
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};
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&mdio0 {
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status = "okay";
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pinctrl-0 = <&mdio0_pins>;
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pinctrl-names = "default";
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ethernet-phy@0 {
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reg = <0x0>;
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qca,ar8327-initvals = <
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0x00004 0x7600000 /* PAD0_MODE */
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0x00008 0x1000000 /* PAD5_MODE */
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0x0000c 0x80 /* PAD6_MODE */
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0x000e4 0xaa545 /* MAC_POWER_SEL */
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0x000e0 0xc74164de /* SGMII_CTRL */
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0x0007c 0x4e /* PORT0_STATUS */
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0x00094 0x4e /* PORT6_STATUS */
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>;
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};
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phy7: ethernet-phy@7 {
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reg = <7>;
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};
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};
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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qcom,id = <0>;
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nvmem-cells = <&macaddr_fw_env_18>;
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nvmem-cell-names = "mac-address";
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pinctrl-0 = <&rgmii2_pins>;
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pinctrl-names = "default";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&gmac1 {
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status = "okay";
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phy-mode = "sgmii";
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qcom,id = <1>;
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nvmem-cells = <&macaddr_fw_env_0>;
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nvmem-cell-names = "mac-address";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&gmac3 {
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status = "okay";
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phy-mode = "sgmii";
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qcom,id = <3>;
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phy-handle = <&phy7>;
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nvmem-cells = <&macaddr_fw_env_6>;
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nvmem-cell-names = "mac-address";
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};
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&adm_dma {
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status = "okay";
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};
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&usb3_1 {
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status = "okay";
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};
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&pcie0 {
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status = "okay";
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reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&pcie0_pins>;
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pinctrl-names = "default";
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bridge@0,0 {
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reg = <0x00000000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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wifi0: wifi@1,0 {
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compatible = "pci168c,0046";
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reg = <0x00010000 0 0 0 0>;
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nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
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nvmem-cell-names = "pre-calibration", "mac-address";
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};
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};
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};
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&pcie1 {
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status = "okay";
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reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&pcie1_pins>;
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pinctrl-names = "default";
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max-link-speed = <1>;
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bridge@0,0 {
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reg = <0x00000000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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wifi1: wifi@1,0 {
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compatible = "pci168c,0040";
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reg = <0x00010000 0 0 0 0>;
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nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
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nvmem-cell-names = "pre-calibration", "mac-address";
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};
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};
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};
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@ -65,6 +65,19 @@ define Device/ZyXELImage
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append-metadata
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endef
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define Device/arris_tr4400-v2
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$(call Device/LegacyImage)
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DEVICE_VENDOR := Arris
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DEVICE_MODEL := TR4400
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DEVICE_VARIANT := v2
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SOC := qcom-ipq8065
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BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct ath10k-firmware-qca99x0-ct
|
||||
KERNEL_IN_UBI := 1
|
||||
endef
|
||||
TARGET_DEVICES += arris_tr4400-v2
|
||||
|
||||
define Device/askey_rt4230w-rev6
|
||||
$(call Device/LegacyImage)
|
||||
DEVICE_VENDOR := Askey
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
|||
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -908,8 +908,29 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
@@ -908,8 +908,30 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
qcom-ipq4019-ap.dk04.1-c3.dtb \
|
||||
qcom-ipq4019-ap.dk07.1-c1.dtb \
|
||||
qcom-ipq4019-ap.dk07.1-c2.dtb \
|
||||
|
|
@ -33,6 +33,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
|||
+ qcom-ipq8065-nbg6817.dtb \
|
||||
+ qcom-ipq8065-r7800.dtb \
|
||||
+ qcom-ipq8065-rt4230w-rev6.dtb \
|
||||
+ qcom-ipq8065-tr4400-v2.dtb \
|
||||
+ qcom-ipq8065-xr500.dtb \
|
||||
+ qcom-ipq8068-ecw5410.dtb \
|
||||
+ qcom-ipq8068-mr42.dtb \
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
|||
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -956,8 +956,29 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
@@ -956,8 +956,30 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
qcom-ipq4019-ap.dk04.1-c3.dtb \
|
||||
qcom-ipq4019-ap.dk07.1-c1.dtb \
|
||||
qcom-ipq4019-ap.dk07.1-c2.dtb \
|
||||
|
|
@ -32,8 +32,9 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
|||
+ qcom-ipq8064-wxr-2533dhp.dtb \
|
||||
+ qcom-ipq8065-nbg6817.dtb \
|
||||
+ qcom-ipq8065-r7800.dtb \
|
||||
+ qcom-ipq8065-xr500.dtb \
|
||||
+ qcom-ipq8065-rt4230w-rev6.dtb \
|
||||
+ qcom-ipq8065-tr4400-v2.dtb \
|
||||
+ qcom-ipq8065-xr500.dtb \
|
||||
+ qcom-ipq8068-ecw5410.dtb \
|
||||
+ qcom-ipq8068-mr42.dtb \
|
||||
+ qcom-ipq8068-mr52.dtb \
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user