Reorganize dtsi patches with upstream version and drop dtsi in 5.15
files.
Also add an additional upstream patch for hwspinlock support.
Refresh all the dts with needed changes.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This doesn't cause any panic anymore and no regression are observed with
ath10k. Remove this additional patch.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Remove qcom adm Documentation patch that is not needed for the target.
Probably a leftover when the adm bus was added, now merged upstream.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
In preparation for a cleanup of 5.15 patches copy the files dir to 5.10
and 5.15 kernel version.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The CPU port should define the phy-mode and and a PHY phandle or
fixed-link to indicate how the CPU port is connected to the SoC's
Ethernet controller. On xRX200 this is all internal connection, so use
phy-mode = "internal" along with a fixed-link that matches the
definition inside ð0.
Linux 6.0 shows a warning since upstream commit e09e9873152e3f ("net:
dsa: make phylink-related OF properties mandatory on DSA and CPU
ports"). when these properties are missing. Adding the properties
before OpenWrt is updated to Linux 6.0 is harmless.
Suggested-by: Martin Schiller <ms@dev.tdt.de>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
This patch converts networking on Sony NCP-HG100/Cellular to DSA and
re-enables support for the device.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Convert ZTE MF289F device to DSA, re-order network ports to match the
labels on the case and re-enable the device.
Signed-off-by: Dirk Buchwalder <buchwalder@posteo.de>
Reviewed-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Lech Perczak <lech.perczak@gmail.com>
* set correct clocks for PWM to work.
* MT7986 PWM does have the 26MHz-clock-select, set that in patch
* drop useless 'passive' trip point in thermal zone
* extend pwm-fan to have 3 active operating points
* set reasonable trip points in thermal zone
* invert pwm-fan operating points and set shorter period to allow
less noisy operation of the PWM fan of the BPi-R3.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
In *_enable_learning() only address learning should be configured, so
remove enabling forwarding. Forwarding is configured by the respective
*_enable_flood() functions.
Clean up both functions for RTL838x and RTL839x, and fix the comment on
the number of entries.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[squash RTL838x, RTL839x changes]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Those messages should be printed when entry was found (idx >= 0). Move
them to the right place to not print invalid entry indices.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amden commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The initial state of sds_mode in rtl9300_force_sds_mode() is null and it
will be configured in switch-case. So print message after it.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Use the generic function of MIPS in Linux Kernel instead of open coding
our own initialisation.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The availabibity of probing CPC depends on CONFIG_MIPS_CPC symbol and it
will be checked in arch/mips/include/asm/mips-cpc.h. RTL9310 selects
this symbol, so the family check is redudant.
Furthermore, mips_cm_probe() is already called from setup_arch() in
mips/kernel/setup.c before prom_init(), and as such is not required.
Also move mips_cpc_probe() to run just before registering SMP ops.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[squash SMP change commits, reword commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
This patch only really has an impact on the rtl931x subtarget, which has
no devices. Noboby is currently set up to test these patches either, but
the end result is closer to MIPS_GENERIC, so I do not expect it to cause
issues.
RTL8231 and ethernet phys are not on the same bus, so separate the lock
to each own to cut off the unnecessary dependency.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Everywhere else the device is referred to as WS-AP3805i,
only the model name wrongly only said AP3805i.
Signed-off-by: Tom Herbers <mail@tomherbers.de>
Setup thermal zone, select pins and enabled drivers for I2C (on 26-pin
GPIO bank) and PWM (1x fan and 1x GPIO bank).
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add support for hardware I2C and PWM units found in the Filogic SoCs
as well as the CPU thermal support.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This allows the user to specify a larger tx ring buffer size via ethtool.
Having symmetrical ring buffer sizes increases throughput on high bandwidth
(1 gbps tested) network connections.
The default value is not changed so the same behaviour is saved.
Signed-off-by: Robert Meijer <robert.s.meijer@gmail.com>
[ improve title, commit description and wrap to 80 columns ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Convert pakedge_wr-1 device to DSA and enable it.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Reviewed-by: Robert Marko <robimarko@gmail.com>i
[ improve commit description ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Convert luma_wrtq-329acn device to DSA and enable it.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Reviewed-by: Robert Marko <robimarko@gmail.com>
[ improve commit description ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The device has only 1 WAN + 3 LAN ports. Remove "lan4" interface
corresponding to the non-existing port.
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
When testing the DSA changes with 5.15.60 kernel, I've noticed, that the
MAC addresses are not properly configured, there is single MAC being
used for LAN and WAN interfaces:
eth0: 94:83:c4:XX:YY:4a (MAC on sticker)
lan1@eth0: 94:83:c4:XX:YY:4a
lan2@eth0: 94:83:c4:XX:YY:4a
wan@eth0: 94:83:c4:XX:YY:4a
wlan0: 94:83:c4:XX:YY:4a
wlan1: 94:83:c4:XX:YY:4b
The same config, prior to the DSA conversion:
lan/eth0: 94:83:c4:XX:YY:4a (MAC on sticker)
wan/eth1: 94:83:c4:XX:YY:4b
wlan0: 94:83:c4:XX:YY:4a
wlan1: 94:83:c4:XX:YY:4b
Settings in ART partition:
root@OpenWrt:/# hexdump -C /dev/mtd7 | grep '94 83'
00000000 94 83 c4 XX YY 4a 94 83 c4 0e YY 4b ff ff ff ff |.....J.....K....|
00001000 20 2f 8d 8c 01 01 94 83 c4 XX YY 4a 00 00 20 00 | /.........J.. .|
00005000 20 2f 5a 3a 01 01 94 83 c4 XX YY 4b 00 00 20 00 | /Z:.......K.. .|
So let's fix it by keeping same MAC address assigment as was done before
DSA conversion and while at it, define `label-mac-device` as well.
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Remove networking configs for non DSA converted boards in ipq40xx.
Currently, they are just causing clutter.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Enable threaded NAPI by default in IPQESS driver as it significantly
improves network perfromance, in my testing about 100+ Mbps in WAN-LAN
routing.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This fixes assigning random MAC to br-lan interface upon boot.
While at that, rename at24@50 node to eeprom@50, to align with upstream
device tree style.
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Convert IPQ40xx boards to DSA setup.
Signed-off-by: Leon M. George <leon@georgemail.eu>
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Signed-off-by: Nick Hainke <vincent@systemli.org>
Signed-off-by: ChunAm See <z1250747241@gmail.com>
Signed-off-by: Jeff Kletsky <git-commits@allycomm.com>
Signed-off-by: Andrew Sim <andrewsimz@gmail.com>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Serhii and others have experienced PSGMII link degradation up to point
that it actually does not pass packets at all or packets arrive as zeros.
This usually happened after a couple of hot reboots.
Serhii has managed to track it down to PSGMII calibration not being done
properly and has fixed it, so all of the code is Serhii-s work.
Signed-off-by: Serhii Serhieiev <adron@mstnt.com>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Since kernel 5.4 has been droppped from IPQ40xx, there is no need to keep
the version checks for kernels older than 5.10.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Currently, suspend and resume ops are not present, this means that if user
disables a DSA interface that the PHY-s remain alive and the link is up.
Fix it by using generic PHY suspend and resume ops.
Signed-off-by: Serhii Serhieiev <adron@mstnt.com>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Select the Ethernet driver, DSA tag driver and the DSA driver itself to
be built in the kernel config.
They automatically pull in switchdev and phylink.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
It shares most of the stuff with its external counterpart, however it is
modified for the SoC.
Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
instead of 7.
It also has no built-in PHY-s but rather requires external PSGMII based
companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
out calibration before using them.
PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
unfortunately requires some magic values as the datasheet doesnt document
the bits that are being set or the register at all.
Since its built-in it is MMIO like other peripherals and doesn't have its
own MDIO bus but depends on the SoC provided one.
CPU connection is at Port 0 and it uses some kind of a internal connection
and no traditional RGMII/SGMII.
It also doesn't use in-band tagging like other qca8k switches so a shinfo
based tagger is used.
This is based on the current OpenWrt qca8k version that has been imported
from generic target.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This is just importing the qca8k driver from the generic target.
It will be used as the based for IPQ40xx version, this is just
to be able to see the diff.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
PSGMII is a Qualcomm specific mode similar to QSGMII but it has 5 SGMII
lines instead of 4 in QSGMII.
This just adds the support for the PHY layer to be able to identify the
mode for further use.
It is required for the DSA driver.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
IPQESS is the EDMA replacement driver for the IPQ40xx SoC built-in
ethernet controller.
Unlike EDMA it is Phylink based and doesnt touch PHY-s directly.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
There is no point in using a DT property to trigger setting the PSGMII
PHY AZ transmitting ability.
Especially since EEE can be disabled using ethtool anyway.
Fixup the mask for setting the workaround as only BIT(0) is actually being
changed and use the phy_clear_bits_mmd helper instead of reading, then
clearing the bit and writing back as it does everything for us.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
IPQ40xx requires a special DSA tag driver despite using the QCA8337N
switch.
However they have changed the header format and the existing QCA tag
driver cannot be reused.
For details on how it actually works and else read the patch commit
description.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
