Commit Graph

5 Commits

Author SHA1 Message Date
Ansuel Smith
abc17bf306 ath79: convert mtd-mac-address to nvmem implementation
Define nvmem-cells and convert mtd-mac-address to nvmem implementation.
The conversion is done with an automated script.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
2021-07-19 14:51:22 +02:00
Adrian Schmutzler
3a4b751110 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-02-24 02:53:53 +01:00
Adrian Schmutzler
1fb40a72da treewide: use more descriptive names for concatenated partitions
A few devices in ath79 and ramips use mtd-concat to concatenate
individual partitions into a bigger "firmware" or "ubi" partition.

However, the original partitions are still present and visible,
and one can write to them directly although this might break the
actual virtual, concatenated partition.

As we cannot do much about the former, let's at least choose more
descriptive names than just "firmwareX" in order to indicate the
concatenation to the user. He might be less tempted into overwriting
a "fwconcat1" than a "firmware1", which might be perceived as an
alternate firmware for dual boot etc.

This applies the new naming consistently for all relevant devices,
i.e. fwconcatX for virtual "firmware" members and ubiconcatX for
"ubi" members.

While at it, use DT labels and label property consistently, and
also use consistent zero-based indexing.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2020-12-27 20:33:45 +01:00
Tomasz Maciej Nowak
13581a5fa7 ath79: airtight c-75: use second flash chip
The flash capacity is divided in two flash chips and currently only
first is used. Increase available space for OpenWrt by additional 16 MiB
using mtd-concat driver. Because U-Boot might not be able to load kernel
image spanned through two flash chips, the size of kernel is limited
to space available on first first chip.

Cc: Vladimir Georgievsky <vladimir.georgievsky@yahoo.com>
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
2020-12-19 19:42:00 +01:00
Tomasz Maciej Nowak
0d96d36841 ath79: add support for AirTight C-75
AirTight Networks (later renamed to Mojo Networks) C-75 is a dual-band
access point, also sold by WatchGuard under name AP320.

Specification
SoC: Qualcomm Atheros QCA9550
RAM: 128 MiB DDR2
Flash: 2x 16 MiB SPI NOR
WIFI: 2.4 GHz 3T3R integrated
      5 GHz 3T3R QCA9890 oversized Mini PCIe card
Ethernet: 2x 10/100/1000 Mbps QCA8334
          port labeled LAN1 is PoE capable (802.3at)
USB: 1x 2.0
LEDs: 7x which two are GPIO controlled, four switch controlled, one
      controlled by wireless driver
Buttons: 1x GPIO controlled
Serial: RJ-45 port, Cisco pinout
        baud: 115200, parity: none, flow control: none
JTAG: Yes, pins marked J1 on PCB

Installation
1. Prepare TFTP server with OpenWrt initramfs-kernel image.
2. Connect to one of LAN ports.
3. Connect to serial port.
4. Power on the device and when prompted to stop autoboot, hit any key.
5. Adjust "ipaddr" and "serverip" addresses in U-Boot environment, use
   'setenv' to do that, then run following commands:
    tftpboot 0x81000000 <openwrt_initramfs-kernel_image_name>
    bootm 0x81000000
6. Wait about 1 minute for OpenWrt to boot.
7. Transfer OpenWrt sysupgrade image to /tmp directory and flash it
   with:
    sysupgrade -n /tmp/<openwrt_sysupgrade_image_name>
8. After flashing, the access point will reboot to OpenWrt. Wait few
   minutes, until the Power LED stops blinking, then it's ready for
   configuration.

Known issues
Green power LED does not work.

Additional information
The U-Boot fails to initialise ethernet ports correctly when a UART
adapter is attached to UART pins (marked J3 on PCB).

Cc: Vladimir Georgievsky <vladimir.georgievsky@yahoo.com>
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
2020-12-19 19:42:00 +01:00