Enable threaded NAPI by default in IPQESS driver as it significantly
improves network perfromance, in my testing about 100+ Mbps in WAN-LAN
routing.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Serhii and others have experienced PSGMII link degradation up to point
that it actually does not pass packets at all or packets arrive as zeros.
This usually happened after a couple of hot reboots.
Serhii has managed to track it down to PSGMII calibration not being done
properly and has fixed it, so all of the code is Serhii-s work.
Signed-off-by: Serhii Serhieiev <adron@mstnt.com>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Since kernel 5.4 has been droppped from IPQ40xx, there is no need to keep
the version checks for kernels older than 5.10.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Currently, suspend and resume ops are not present, this means that if user
disables a DSA interface that the PHY-s remain alive and the link is up.
Fix it by using generic PHY suspend and resume ops.
Signed-off-by: Serhii Serhieiev <adron@mstnt.com>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
It shares most of the stuff with its external counterpart, however it is
modified for the SoC.
Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
instead of 7.
It also has no built-in PHY-s but rather requires external PSGMII based
companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
out calibration before using them.
PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
unfortunately requires some magic values as the datasheet doesnt document
the bits that are being set or the register at all.
Since its built-in it is MMIO like other peripherals and doesn't have its
own MDIO bus but depends on the SoC provided one.
CPU connection is at Port 0 and it uses some kind of a internal connection
and no traditional RGMII/SGMII.
It also doesn't use in-band tagging like other qca8k switches so a shinfo
based tagger is used.
This is based on the current OpenWrt qca8k version that has been imported
from generic target.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This is just importing the qca8k driver from the generic target.
It will be used as the based for IPQ40xx version, this is just
to be able to see the diff.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
IPQESS is the EDMA replacement driver for the IPQ40xx SoC built-in
ethernet controller.
Unlike EDMA it is Phylink based and doesnt touch PHY-s directly.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
There is no point in using a DT property to trigger setting the PSGMII
PHY AZ transmitting ability.
Especially since EEE can be disabled using ethtool anyway.
Fixup the mask for setting the workaround as only BIT(0) is actually being
changed and use the phy_clear_bits_mmd helper instead of reading, then
clearing the bit and writing back as it does everything for us.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Currently, QCA807x doesnt do any kind of validation to see whether it
actually supports the inserted module.
So lets add checks to allow only 1000BaseX and 100BaseFX based modules.
While adding validation, move fiber configuration to insert/remove events
instead of always doing it at config time.
This allows getting rid of the DT property for fiber enable and now only
the upstream sfp phandle is required.
Since we are refactoring fiber related code, lets heavily simplify the
status polling as the current logic is overcomplicated due to previous
wish to support non standard SFP cages that dont have pins properly
connected, that is removed now and only proper SFP cages will work.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
In order to start working on IPQESS + DSA drop the old ESSEDMA + AR40xx
driver combo.
Remove the kernel symbols, disable swconfig and drop swconfig package
as they are not needed anymore.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Commit f4fb63d2ab ("ipq40xx: 5.10: move AR40xx to MDIO drivers") moved
the ar40xx driver files to kernel version specific directories to place
them in different subdirectory in kernel tree. But now kernel 5.4 is
gone and there is no reason to keep them separate. Move them back to
common files/ directory.
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
Kernel 5.15 have some new api for ethtool and phy.
Add ifdef to fix compilation error.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Robert Marko <robert.marko@sartura.hr>
MDIO drivers were moved into their own sub directory of networking drivers.
This has caused the AR40xx driver to probe before MDIO drivers and that wont
work as it depends on the MDIO bus to be up so it can be fetched.
Lets solve it by moving the AR40xx into MDIO folder so they get probed like
before.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Set ethtool_ops->supported_coalesce_params to let
the core reject unsupported coalescing parameters.
This driver did not previously reject unsupported parameters.
This is a required ethtool op since kernel 5.7.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
In kernel v5.5 of_get_phy_mode had its API changed, so its now returning 0
or errors instead of phymode.
Phymode is now returning by passing a pointer to phy_interface_t where it
will be stored.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This resolves incosnsitencies of the configured RX / TX flow control
modes between different boards or bootloaders.
Signed-off-by: David Bauer <mail@david-bauer.net>
In the current state, nvmem cells are only detected on platform device.
To quickly fix the problem, we register the affected problematic driver
with the of_platform but that is more an hack than a real solution.
Backport from net-next the required patch so that nvmem can work also
with non-platform devices and rework our current patch.
Drop the mediatek and dsa workaround and rework the ath10k patches.
Rework every driver that use the of_get_mac_address api.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
While rebasing into setting bits instead of magic values,
I accidentally forgot to actually set the force bit.
Without it using the pins as GPIO-s did not actually work.
Fixes: b5c93ed ("ipq40xx: add Qualcomm QCA807x driver")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Lets use the generic upstream phy_print_status() instead of doing
something similar by hand.
Before:
ess_edma c080000.edma: eth1: GMAC Link is up with phy_speed=1000
After:
ess_edma c080000.edma eth1: Link is Up - 1Gbps/Full - flow control rx/tx
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Since we now have a proper PHY driver for QCA807x and AR803x has already
been supported properly there is no need for the driver to be poking
on PHY registers for ethtool ops.
So, lets simply use the generic
phy_ethtool_ksettings_get/phy_ethtool_ksettings_set functions.
This also has the advantage of properly populating stuff other than
speeds like, transceiver type, MDI-X etc.
ethtool before:
root@OpenWrt:/# ethtool eth1
Settings for eth1:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseX/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseX/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Link partner advertised pause frame use: No
Link partner advertised auto-negotiation: No
Link partner advertised FEC modes: Not reported
Speed: 1000Mb/s
Duplex: Full
Port: Twisted Pair
PHYAD: 4
Transceiver: internal
Auto-negotiation: on
MDI-X: Unknown
Supports Wake-on: d
Wake-on: d
Current message level: 0x00000000 (0)
Link detected: yes
ethtool after:
root@OpenWrt:/# ethtool eth1
Settings for eth1:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseX/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseX/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Link partner advertised pause frame use: Symmetric Receive-only
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 1000Mb/s
Duplex: Full
Port: Twisted Pair
PHYAD: 4
Transceiver: external
Auto-negotiation: on
MDI-X: off (auto)
Supports Wake-on: d
Wake-on: d
Current message level: 0x00000000 (0)
Link detected: yes
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
PHY needs to be soft reset before starting it from ethernet driver as
AR40xx calibration will leave it in unwanted state.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Since we now have proper PHY driver for the QCA807x PHY-s, lets remove
PHY handling from AR40xx.
This removes PHY driver, PHY GPIO driver and PHY init code.
AR40xx still needs to handle PSGMII calibration as that requires R/W
from the switch, so I am unable to move it into PHY driver.
This also converted the AR40xx driver to use OF_MDIO to find the MDIO
bus as it now cant be set through the PHY driver.
So lets depend on OF_MDIO in KConfig.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
They are 2 or 5 port IEEE 802.3 clause 22 compliant
10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.
They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC,
while second one is SGMII for connection to MAC or fiber.
Both models have a combo port that supports 1000BASE-X and 100BASE-FX
fiber.
Each PHY inside of QCA807x series has 2 digitally controlled output only
pins that natively drive LED-s.
But some vendors used these to driver generic LED-s controlled by
user space, so lets enable registering each PHY as GPIO controller and
add driver for it.
This also adds the ability to specify DT properties so that 1000 Base-T
LED will also be lit up for 100 and 10 Base connections.
This is usually done by U-boot, but boards running mainline U-boot are
not configuring this yet.
These PHY-s are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x
boards.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
With the reworked MDIO driver, EDMA will fail to get the MII BUS as it
used the MII BUS stored inside the MDIO structure private data.
This obviously does not work with the modernized driver, so lets switch
to using a purpose build of_mdio_find_bus() which will return the MII
BUS and only requires the MDIO node to be passed.
This is easy as we already have the node parsed.
Also, since we now require OF_MDIO add that as dependency.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This reverts the usage of the S-Tag for separating LAN and WAN port on
the embedded switch. Many users complained about not being able to
manage C-Tag addition / removal on the switch as well as degraded
performance.
Fixes: commit 9da2b56760 ("ipq40xx: fix ethernet vlan double tagging")
Signed-off-by: David Bauer <mail@david-bauer.net>
This re-enables offloading features disabled by
commit 9da2b56760 ("ipq40xx: fix ethernet vlan double tagging").
Single-PHY devices use port-based VLANs on the switch, therefore no
S-TAG magic is involved here. Re-enabling these features restores
throughput back to 950 Mbit/s.
Reported-by: Jannis Pinter <jannis@pinterjann.is>
Signed-off-by: David Bauer <mail@david-bauer.net>
The target uses 5.4 as default kernel since 03/2020.
Kernel 4.19 support is not really maintained anymore, it does not
seem to be needed, and removing it will make upcoming driver
updates easier. Thus, remove it.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
