Commit Graph

19 Commits

Author SHA1 Message Date
Chuanhong Guo
ebf0d8dade ath79: add new ar934x spi driver
A new shift mode was introduced since ar934x which has a way better
performance than current bitbang driver and can handle higher spi
clock properly. This commit adds a new driver to make use of this
new feature.
This new driver has chipselect properly configured and we don't need
cs-gpios hack in dts anymore. Remove them.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2020-02-06 22:53:03 +08:00
David Bauer
a8a9340609 ath79: fix incorrect identation in qca9557.dtsi
Signed-off-by: David Bauer <mail@david-bauer.net>
2019-10-27 18:03:56 +01:00
André Valentin
99835e0999 ath79: add support for ZyXEL NBG6716
Attention: Kernel partition size has been enlarged to 4MB.
To switch, you must update to latest ar71xx-nand snapshort and flash the
sysupgrade-4M-Kernel.bin:

zcat openwrt-ath79-nand-zyxel_nbg6716-squashfs-sysupgrade-4M-Kernel.bin | mtd -r -e ubi write - firmware; reboot -f
You will end up with a fresh config if you do not inject config into the image.

The NBG6716 may come with 128MB or 256MB NAND. ar71xx was able to use all, but
ath79 can only use the first 128MB. Therefore the complete NAND needs to be
overwritten. If not, the old UBI may make problems and lead to reboot loop.

Access the real u-boot shell:
ZyXEL uses a proprietary loader/shell on top of u-boot: "ZyXEL zloader v2.02"
When the device is starting up, the user can enter the the loader shell
by simply pressing a key within the 3 seconds once the following string
appears on the serial console:

|   Hit any key to stop autoboot:  3

The user is then dropped to a locked shell.

|NBG6716> HELP
|ATEN    x[,y]     set BootExtension Debug Flag (y=password)
|ATSE    x         show the seed of password generator
|ATSH              dump manufacturer related data in ROM
|ATRT    [x,y,z,u] RAM read/write test (x=level, y=start addr, z=end addr, u=iterations)
|ATGO              boot up whole system
|ATUR    x         upgrade RAS image (filename)
|NBG6716>

In order to escape/unlock a password challenge has to be passed.
Note: the value is dynamic! you have to calculate your own!

First use ATSE $MODELNAME (MODELNAME is the hostname in u-boot env)
to get the challange value/seed.

|NBG6716> ATSE NBG6716
|012345678901

This seed/value can be converted to the password with the help of this
bash script (Thanks to http://www.adslayuda.com/Zyxel650-9.html authors):

- tool.sh -
ror32() {
  echo $(( ($1 >> $2) | (($1 << (32 - $2) & (2**32-1)) ) ))
}
v="0x$1"
a="0x${v:2:6}"
b=$(( $a + 0x10F0A563))
c=$(( 0x${v:12:14} & 7 ))
p=$(( $(ror32 $b $c) ^ $a ))
printf "ATEN 1,%X\n" $p
- end of tool.sh -

|# bash ./tool.sh 012345678901
|
|ATEN 1,879C711

copy and paste the result into the shell to unlock zloader.

|NBG6716> ATEN 1,0046B0017430

If the entered code was correct the shell will change to
use the ATGU command to enter the real u-boot shell.

|NBG6716> ATGU
|NBG6716#

Signed-off-by: André Valentin <avalentin@marcant.net>
2019-10-27 13:38:49 +01:00
Chuanhong Guo
f65501e1c2 ath79: ar93xx/qca95xx: move gmac/wmac/pcie node out of apb bus
according to functional block diagram in datasheet, these devices
don't belong to apb bus.
Move these nodes out to match datasheet description.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2019-07-16 09:52:43 +08:00
David Bauer
b8236e102c ath79: fix QCA955x GMAC register size
The register size of the QCA955x currently matches the size stated in
the datasheet. However, there are more hidden GMAC registers which are
needed for the SGMII workaround to work.

Signed-off-by: David Bauer <mail@david-bauer.net>
2019-06-02 11:08:37 +02:00
Chuanhong Guo
47f0be676f ath79: qca955x: assert mdio/gmac reset together
This allows resetting gmac registers during initialization.
Also add compatible string for qca955x mdio to enable more mdio
clock dividers.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2019-03-05 03:02:34 +01:00
Santiago Piccinini
cc8bd77772 ath79: fix qca955x dual pci resource allocation
Tested with a dual pci QCA9558 board (LibreRouter v1) in three
configurations: enabling pcie0 only, pcie1 only and both enabled.

Signed-off-by: Santiago Piccinini <spiccinini@altermundi.net>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com> [removed ML notice]
2019-02-14 16:56:15 +01:00
Santiago Piccinini
eea66c3227 ath79: fix qca955x pcie0 memory size
Datasheet states that both PCI ranges are of 0x2000000 size:
0x1000_0000-0x11FF_FFF and 0x1200_0000-0x13FF_0000.

Signed-off-by: Santiago Piccinini <spiccinini@altermundi.net>
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com> [removed ML notice]
2019-02-14 16:56:15 +01:00
Christian Lamparter
87c5fd348d ath79: fix pinmux reg size for QCA955x
The range of pinmux reg property "<0x1804002c 0x40>" for QCA955x
SoC does not includes GPIO_FUNCTION register.

Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2018-12-24 19:18:07 +01:00
Mathias Kresin
0fdfdaef2d ath79: fix dtc compiler warnings
The qca9557/qca956x reset-controller aren't a simple bus. A simple bus
would require node unit addresses.

Add the node unit addresses for the qca9557 usb phys. Add the regs for
the USB_PWRCTL and USB_CONFIG registers even not yet used.

Fix the wrong ar7100 pcie controller node unit address as well.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2018-12-12 12:28:26 +01:00
David Bauer
6555612783 ath79: fix PLL settings for QCA955x
This adds PLL settings for the ethernet ports of the TP-Link TL-WR1043
v2/v3 and the Openmesh OM5P-AC-v2.

We also change the PLL-settings in the qca9557.dtsi to match the ones
used as default on the ar71xx target.

As of 4b9680f138 those devices have broken ethernet ports as the default
PLL settings defined in the QCA9557.dtsi are applied which are off for
those devices.

Signed-off-by: David Bauer <mail@david-bauer.net>
2018-08-09 17:24:39 +01:00
David Bauer
4b9680f138 ath79: fix QCA9557 eth PLL settings
The QCA9557 dtsi is currently missing pll-handle and pll-regs for both
eth0 and eth1, therefore PLL settings won't be applied. This commit
fixes this behavior.

Signed-off-by: David Bauer <mail@david-bauer.net>
2018-08-08 08:38:45 +02:00
Mathias Kresin
55ff2951ea ath79: fix dts warnings
Fix all issues found by the devicetree compiler like wrong address/size
cells as well as wrong/missing/superfluous unit addresses.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2018-08-08 08:11:11 +02:00
Chuanhong Guo
18db385eb7 ath79: qca955x: Update dts for current ag71xx driver
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-07-30 10:43:34 +02:00
Chuanhong Guo
2d081addb5 ath79: ag71xx: Split gmac config into separated file and add support for ar934x/qca955x.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-07-30 10:43:33 +02:00
Johann Neuhauser
b8562f168b ath79: qca95xx: add new intc2, correct intc3 and add second pcie on qca9557
Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
2018-06-20 11:12:00 +02:00
Lucian Cristian
b1a173d7c3 ath79: add support for tl-wr1043nd v2/v3
Signed-off-by: Lucian Cristian <lucian.cristian@gmail.com>
2018-06-18 20:29:38 +02:00
Rafał Miłecki
66c8afd115 ath79: relicense DTS files to the GPL 2.0+ / MIT
Some maintainers prefer DTS files licensed under permissive license like
MIT / BSD. As all DT bindings should be OS independent and DTS files are
pretty separated from Linux code it probably makes sense to share them
across projects.

The safest solution is to use dual licensing: that way it stays clear
these files can be used in GPL projects without depending on current
belief of licenses compatibility.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: John Crispin <john@phrozen.org>
2018-05-07 10:31:35 +02:00
John Crispin
53c474abbd ath79: add new OF only target for QCA MIPS silicon
This target aims to replace ar71xx mid-term. The big part that is still
missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik
subtargets will follow.

Signed-off-by: John Crispin <john@phrozen.org>
2018-05-07 08:06:51 +02:00