d55c087390
The TP-Link RTL83xx based switches have their MAC address programmed in the "para" partition. While in theory, the format of this partition is dynamic, in practice, the MAC address appears to be located at a consistent address. Thus, use nvmem-cells to read this MAC address. The main MAC is required for deriving the MAC address of the switch ports. Instead of reading it via mtd_get_mac_binary(), alias the ethernet0 node as the label-mac-device, and use get_mac_label(). Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
423 lines
8.2 KiB
Plaintext
423 lines
8.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl839x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "tplink,sg2452p-v4", "realtek,rtl8393-soc";
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model = "TP-Link SG2452P v4";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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label-mac-device = ðernet0;
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};
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chosen {
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bootargs = "console=ttyS0,38400";
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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speed {
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label = "speed";
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gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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};
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gpio_fan_sys {
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compatible = "gpio-fan";
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alarm-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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};
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gpio_fan_psu_1 {
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pinctrl-names = "default";
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pinctrl-0 = <&disable_jtag>;
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compatible = "gpio-fan";
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alarm-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
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gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
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/* the actual speeds (rpm) are unknown, just use dummy values */
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gpio-fan,speed-map = <1 0>, <2 1>;
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#cooling-cells = <2>;
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};
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gpio_fan_psu_2 {
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/* This fan runs in parallel to PSU1 fan, but has a separate
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* alarm GPIO. This is not (yet) supported by the gpio-fan driver,
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* so a separate instance is added
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*/
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compatible = "gpio-fan";
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alarm-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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leds {
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pinctrl-names = "default";
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compatible = "gpio-leds";
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led-0 {
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label = "green:speed";
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gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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};
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led-1 {
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label = "green:poe";
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gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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};
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led_sys: led-2 {
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label = "green:sys";
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gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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};
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led-3 {
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label = "green:fan";
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gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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};
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led-4 {
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label = "amber:fan";
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gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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function = "fault-fan";
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};
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led-5 {
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label = "green:poe-max";
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gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = "alarm-poe";
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};
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};
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i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* LAN9 - LAN12 */
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tps23861@5 {
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compatible = "ti,tps23861";
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reg = <0x05>;
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};
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/* LAN17 - LAN20 */
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tps23861@6 {
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compatible = "ti,tps23861";
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reg = <0x06>;
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};
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/* LAN45 - LAN48 */
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tps23861@9 {
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compatible = "ti,tps23861";
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reg = <0x09>;
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};
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/* LAN37 - LAN40 */
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tps23861@a {
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compatible = "ti,tps23861";
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reg = <0x0a>;
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};
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/* LAN1 - LAN4 */
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tps23861@14 {
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compatible = "ti,tps23861";
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reg = <0x14>;
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};
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/* LAN25 - LAN28 */
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tps23861@24 {
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compatible = "ti,tps23861";
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reg = <0x24>;
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};
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/* LAN33 - LAN 36 */
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tps23861@25 {
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compatible = "ti,tps23861";
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reg = <0x25>;
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};
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/* LAN41 - LAN44 */
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tps23861@26 {
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compatible = "ti,tps23861";
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reg = <0x26>;
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};
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/* LAN13 - LAN16 */
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tps23861@29 {
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compatible = "ti,tps23861";
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reg = <0x29>;
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};
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/* LAN29 - LAN32 */
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tps23861@2c {
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compatible = "ti,tps23861";
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reg = <0x2c>;
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};
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/* LAN5 - LAN8 */
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tps23861@48 {
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compatible = "ti,tps23861";
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reg = <0x48>;
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};
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/* LAN21 - LAN24 */
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tps23861@49 {
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compatible = "ti,tps23861";
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reg = <0x49>;
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};
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
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};
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};
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&gpio0 {
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poe-enable {
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gpio-hog;
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gpios = <23 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "poe-enable";
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0xe0000>;
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read-only;
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};
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partition@e0000 {
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label = "u-boot-env";
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reg = <0xe0000 0x20000>;
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};
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/* We use the "sys", "usrimg1" and "usrimg2" partitions
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* as firmware since the kernel needs to be in "sys", but the
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* partition is too small to hold the "rootfs" as well.
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* The original partition map contains:
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*
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* partition@100000 {
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* label = "sys";
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* reg = <0x100000 0x600000>;
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* };
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* partition@700000 {
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* label = "usrimg1";
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* reg = <0x700000 0xa00000>;
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* };
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* partition@1100000 {
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* label = "usrimg2";
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* reg = <0x1100000 0xa00000>;
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* };
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*/
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partition@100000 {
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label = "firmware";
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reg = <0x100000 0x1a00000>;
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};
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partition@1b00000 {
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label = "usrappfs";
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reg = <0x1b00000 0x400000>;
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};
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partition@1f00000 {
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compatible = "nvmem-cells";
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label = "para";
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reg = <0x1f00000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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read-only;
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factory_macaddr: macaddr@fdff4 {
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reg = <0xfdff4 0x6>;
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};
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};
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};
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};
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};
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ðernet0 {
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nvmem-cells = <&factory_macaddr>;
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nvmem-cell-names = "mac-address";
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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/* External phy RTL8218B #1 */
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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/* External phy RTL8218B #2 */
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EXTERNAL_PHY(8)
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EXTERNAL_PHY(9)
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EXTERNAL_PHY(10)
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EXTERNAL_PHY(11)
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EXTERNAL_PHY(12)
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EXTERNAL_PHY(13)
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EXTERNAL_PHY(14)
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EXTERNAL_PHY(15)
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/* External phy RTL8218B #3 */
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EXTERNAL_PHY(16)
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EXTERNAL_PHY(17)
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EXTERNAL_PHY(18)
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EXTERNAL_PHY(19)
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EXTERNAL_PHY(20)
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EXTERNAL_PHY(21)
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EXTERNAL_PHY(22)
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EXTERNAL_PHY(23)
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/* External phy RTL8218B #4 */
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EXTERNAL_PHY(24)
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EXTERNAL_PHY(25)
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EXTERNAL_PHY(26)
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EXTERNAL_PHY(27)
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EXTERNAL_PHY(28)
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EXTERNAL_PHY(29)
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EXTERNAL_PHY(30)
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EXTERNAL_PHY(31)
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/* External phy RTL8218B #5 */
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EXTERNAL_PHY(32)
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EXTERNAL_PHY(33)
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EXTERNAL_PHY(34)
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EXTERNAL_PHY(35)
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EXTERNAL_PHY(36)
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EXTERNAL_PHY(37)
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EXTERNAL_PHY(38)
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EXTERNAL_PHY(39)
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/* External phy RTL8218B #6 */
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EXTERNAL_PHY(40)
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EXTERNAL_PHY(41)
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EXTERNAL_PHY(42)
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EXTERNAL_PHY(43)
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EXTERNAL_PHY(44)
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EXTERNAL_PHY(45)
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EXTERNAL_PHY(46)
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EXTERNAL_PHY(47)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(0, 01, qsgmii)
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SWITCH_PORT(1, 02, qsgmii)
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SWITCH_PORT(2, 03, qsgmii)
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SWITCH_PORT(3, 04, qsgmii)
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SWITCH_PORT(4, 05, qsgmii)
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SWITCH_PORT(5, 06, qsgmii)
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SWITCH_PORT(6, 07, qsgmii)
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SWITCH_PORT(7, 08, qsgmii)
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SWITCH_PORT(8, 09, qsgmii)
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SWITCH_PORT(9, 10, qsgmii)
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SWITCH_PORT(10, 11, qsgmii)
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SWITCH_PORT(11, 12, qsgmii)
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SWITCH_PORT(12, 13, qsgmii)
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SWITCH_PORT(13, 14, qsgmii)
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SWITCH_PORT(14, 15, qsgmii)
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SWITCH_PORT(15, 16, qsgmii)
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SWITCH_PORT(16, 17, qsgmii)
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SWITCH_PORT(17, 18, qsgmii)
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SWITCH_PORT(18, 19, qsgmii)
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SWITCH_PORT(19, 20, qsgmii)
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SWITCH_PORT(20, 21, qsgmii)
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SWITCH_PORT(21, 22, qsgmii)
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SWITCH_PORT(22, 23, qsgmii)
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SWITCH_PORT(23, 24, qsgmii)
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SWITCH_PORT(24, 25, qsgmii)
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SWITCH_PORT(25, 26, qsgmii)
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SWITCH_PORT(26, 27, qsgmii)
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SWITCH_PORT(27, 28, qsgmii)
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SWITCH_PORT(28, 29, qsgmii)
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SWITCH_PORT(29, 30, qsgmii)
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SWITCH_PORT(30, 31, qsgmii)
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SWITCH_PORT(31, 32, qsgmii)
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SWITCH_PORT(32, 33, qsgmii)
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SWITCH_PORT(33, 34, qsgmii)
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SWITCH_PORT(34, 35, qsgmii)
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SWITCH_PORT(35, 36, qsgmii)
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SWITCH_PORT(36, 37, qsgmii)
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SWITCH_PORT(37, 38, qsgmii)
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SWITCH_PORT(38, 39, qsgmii)
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SWITCH_PORT(39, 40, qsgmii)
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SWITCH_PORT(40, 41, qsgmii)
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SWITCH_PORT(41, 42, qsgmii)
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SWITCH_PORT(42, 43, qsgmii)
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SWITCH_PORT(43, 44, qsgmii)
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SWITCH_PORT(44, 45, qsgmii)
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SWITCH_PORT(45, 46, qsgmii)
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SWITCH_PORT(46, 47, qsgmii)
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SWITCH_PORT(47, 48, qsgmii)
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/* CPU-Port */
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port@52 {
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ethernet = <ðernet0>;
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reg = <52>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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