tn3399_openwrt/target/linux/ath79/dts/ar7100.dtsi
David Bauer 0494278073 ath79: resolve GPIO address conflicts
The ar71xx GPIO driver only uses 0x24 registers, all following GPIO
registers are using to control pinmux functions, which are not handles
by the GPIO driver but the generic Linux pinctrl driver.

For some SoC conflicting address ranges were defined for these (AR7240 &
AR9330).

Resolve these cases and align the address space of the GPIO controller
between all SoCs, as the used address space of the driver is identical
for all these.

Signed-off-by: David Bauer <mail@david-bauer.net>
2021-07-01 23:26:49 +02:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ath79.dtsi"
/ {
compatible = "qca,ar7100";
chosen {
bootargs = "console=ttyS0,115200";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "mips,mips24Kc";
clocks = <&pll ATH79_CLK_CPU>;
reg = <0>;
};
};
ahb {
apb {
ddr_ctrl: memory-controller@18000000 {
compatible = "qca,ar7100-ddr-controller";
reg = <0x18000000 0x100>;
#qca,ddr-wb-channel-cells = <1>;
};
uart: uart@18020000 {
compatible = "ns16550a";
reg = <0x18020000 0x20>;
interrupts = <3>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "uart";
reg-io-width = <4>;
reg-shift = <2>;
no-loopback-test;
};
usb_phy: usb-phy@18030000 {
compatible = "qca,ar7100-usb-phy";
reg = <0x18030000 0x10>;
reset-names = "usb-phy", "usb-host", "usb-ohci-dll";
resets = <&rst 4>, <&rst 5>, <&rst 6>;
#phy-cells = <0>;
status = "disabled";
};
gpio: gpio@18040000 {
compatible = "qca,ar7100-gpio";
reg = <0x18040000 0x28>;
interrupts = <2>;
ngpios = <16>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pll: pll-controller@18050000 {
compatible = "qca,ar7100-pll", "syscon";
reg = <0x18050000 0x20>;
clock-names = "ref";
/* The board must provides the ref clock */
#clock-cells = <1>;
clock-output-names = "cpu", "ddr", "ahb";
};
wdt: wdt@18060008 {
compatible = "qca,ar7130-wdt";
reg = <0x18060008 0x8>;
interrupts = <4>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "wdt";
};
pci_intc: interrupt-controller@18060018 {
compatible = "qca,ar7100-misc-intc";
reg = <0x18060018 0x4>;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
rst: reset-controller@18060024 {
compatible = "qca,ar7100-reset";
reg = <0x18060024 0x4>;
#reset-cells = <1>;
};
pcie0: pcie-controller@17010000 {
compatible = "qca,ar7100-pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0x0>;
reg = <0x17010000 0x100>;
reg-names = "cfg_base";
ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 /* pci memory */
0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
device_type = "pci";
interrupt-parent = <&pci_intc>;
interrupts = <4>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 0>;
interrupt-map = <0x8800 0 0 0 &pci_intc 0
0x9000 0 0 0 &pci_intc 1
0x9800 0 0 0 &pci_intc 2>;
status = "disabled";
};
};
};
usb2: usb@1b000000 {
compatible = "generic-ehci";
reg = <0x1b000000 0x1000>;
interrupt-parent = <&cpuintc>;
interrupts = <3>;
phy-names = "usb-phy";
phys = <&usb_phy>;
has-synopsys-hc-bug;
status = "disabled";
};
usb1: usb@1c000000 {
compatible = "generic-ohci";
reg = <0x1c000000 0x1000>;
interrupt-parent = <&miscintc>;
interrupts = <6>;
phy-names = "usb-phy";
phys = <&usb_phy>;
status = "disabled";
};
spi: spi@1f000000 {
compatible = "qca,ar7100-spi";
reg = <0x1f000000 0x10>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "ahb";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
&cpuintc {
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
};
&miscintc {
compatible = "qca,ar7100-misc-intc";
};
&eth0 {
compatible = "qca,ar7100-eth", "syscon";
reg = <0x19000000 0x200
0x18070000 0x4>;
pll-data = <0x00110000 0x00001099 0x00991099>;
pll-reg = <0x4 0x10 17>;
pll-handle = <&pll>;
phy-mode = "rgmii";
resets = <&rst 9>;
reset-names = "mac";
qca,mac-idx = <0>;
};
&mdio1 {
builtin-switch;
};
&eth1 {
compatible = "qca,ar7100-eth", "syscon";
reg = <0x1a000000 0x200
0x18070004 0x4>;
pll-data = <0x00110000 0x00001099 0x00991099>;
pll-reg = <0x4 0x14 19>;
pll-handle = <&pll>;
phy-mode = "rgmii";
resets = <&rst 13>;
reset-names = "mac";
qca,mac-idx = <1>;
};