tn3399_openwrt/target/linux/ath79/dts/qca9563_tplink_archer-x7-v5.dtsi
Adrian Schmutzler 3a4b751110 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-02-24 02:53:53 +01:00

175 lines
2.8 KiB
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca956x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
led-boot = &led_system;
led-failsafe = &led_system;
led-running = &led_system;
led-upgrade = &led_system;
label-mac-device = &eth0;
};
leds {
compatible = "gpio-leds";
led_system: system {
label = "green:system";
gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
default-state = "on";
};
usb {
label = "green:usb";
gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
trigger-sources = <&hub_port0>;
linux,default-trigger = "usbport";
};
wlan5g {
label = "green:wlan5g";
gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wlan2g {
label = "green:wlan2g";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
wan {
label = "green:wan";
gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
};
wan_fail {
label = "orange:wan";
gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
};
lan1 {
label = "green:lan1";
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
};
lan2 {
label = "green:lan2";
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
};
lan3 {
label = "green:lan3";
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
lan4 {
label = "green:lan4";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
wps {
label = "green:wps";
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
};
keys: keys {
compatible = "gpio-keys";
wps {
label = "WPS button";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
gpio-export {
compatible = "gpio-export";
gpio_usb_power {
gpio-export,name = "tp-link:power:usb";
gpio-export,output = <1>;
gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
};
};
};
&pcie {
status = "okay";
};
&usb_phy0 {
status = "okay";
};
&usb0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
hub_port0: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
mtdparts: partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};
&mdio0 {
status = "okay";
phy-mask = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
phy-mode = "sgmii";
qca,mib-poll-interval = <500>;
qca,ar8327-initvals = <
0x04 0x80080080 /* PORT0 PAD MODE CTRL */
0x08 0x00000000 /* PORT5 PAD MODE CTRL */
0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
0x10 0x00000080 /* POWER_ON_STRAP */
0x7c 0x0000007e /* PORT0_STATUS */
0x94 0x00000200 /* PORT6_STATUS */
>;
};
};
&eth0 {
status = "okay";
pll-data = <0x03000101 0x00000101 0x00001919>;
phy-mode = "sgmii";
mtd-mac-address = <&info 0x8>;
phy-handle = <&phy0>;
};
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
mtd-mac-address = <&info 0x8>;
};