cd619eeff2
Replace gcc patch fixes with upstream version. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
110 lines
3.4 KiB
Diff
110 lines
3.4 KiB
Diff
From e95e825333eda345d812b461301dad50021d5487 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Sat, 26 Feb 2022 14:52:24 +0100
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Subject: [PATCH 04/14] clk: qcom: gcc-ipq806x: fix wrong naming for
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gcc_pxo_pll8_pll0
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Parent gcc_pxo_pll8_pll0 had the parent definition and parent map
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swapped. Fix this naming error.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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Tested-by: Jonathan McDowell <noodles@earth.li>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220226135235.10051-5-ansuelsmth@gmail.com
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---
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drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++----------
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1 file changed, 10 insertions(+), 10 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq806x.c
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+++ b/drivers/clk/qcom/gcc-ipq806x.c
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@@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[]
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"pll3",
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};
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-static const struct parent_map gcc_pxo_pll8_pll0[] = {
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+static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
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{ P_PXO, 0 },
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{ P_PLL8, 3 },
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{ P_PLL0, 2 }
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};
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-static const char * const gcc_pxo_pll8_pll0_map[] = {
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+static const char * const gcc_pxo_pll8_pll0[] = {
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"pxo",
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"pll8_vote",
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"pll0_vote",
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@@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_s
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},
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.s = {
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.src_sel_shift = 0,
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- .parent_map = gcc_pxo_pll8_pll0,
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+ .parent_map = gcc_pxo_pll8_pll0_map,
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},
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.freq_tbl = clk_tbl_usb30_master,
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.clkr = {
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@@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_s
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "usb30_master_ref_src",
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- .parent_names = gcc_pxo_pll8_pll0_map,
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+ .parent_names = gcc_pxo_pll8_pll0,
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.num_parents = 3,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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@@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = {
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},
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.s = {
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.src_sel_shift = 0,
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- .parent_map = gcc_pxo_pll8_pll0,
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+ .parent_map = gcc_pxo_pll8_pll0_map,
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},
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.freq_tbl = clk_tbl_usb30_utmi,
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.clkr = {
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@@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = {
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "usb30_utmi_clk",
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- .parent_names = gcc_pxo_pll8_pll0_map,
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+ .parent_names = gcc_pxo_pll8_pll0,
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.num_parents = 3,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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@@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s
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},
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.s = {
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.src_sel_shift = 0,
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- .parent_map = gcc_pxo_pll8_pll0,
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+ .parent_map = gcc_pxo_pll8_pll0_map,
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},
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.freq_tbl = clk_tbl_usb,
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.clkr = {
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@@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "usb_hs1_xcvr_src",
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- .parent_names = gcc_pxo_pll8_pll0_map,
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+ .parent_names = gcc_pxo_pll8_pll0,
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.num_parents = 3,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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@@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s
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},
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.s = {
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.src_sel_shift = 0,
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- .parent_map = gcc_pxo_pll8_pll0,
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+ .parent_map = gcc_pxo_pll8_pll0_map,
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},
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.freq_tbl = clk_tbl_usb,
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.clkr = {
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@@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "usb_fs1_xcvr_src",
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- .parent_names = gcc_pxo_pll8_pll0_map,
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+ .parent_names = gcc_pxo_pll8_pll0,
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.num_parents = 3,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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