cd619eeff2
Replace gcc patch fixes with upstream version. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
89 lines
2.9 KiB
Diff
89 lines
2.9 KiB
Diff
From 512ea2edfe15ffa2cd839b3a31d768145f2edc20 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Sat, 26 Feb 2022 14:52:27 +0100
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Subject: [PATCH 07/14] clk: qcom: gcc-ipq806x: add additional freq nss cores
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Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be
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clocked to 800MHz. Add these missing freq to the gcc driver.
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Set the freq_tbl for the ubi32_cores to the correct values based on the
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machine compatible.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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Tested-by: Jonathan McDowell <noodles@earth.li>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220226135235.10051-8-ansuelsmth@gmail.com
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---
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drivers/clk/qcom/gcc-ipq806x.c | 24 +++++++++++++++++++++---
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1 file changed, 21 insertions(+), 3 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq806x.c
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+++ b/drivers/clk/qcom/gcc-ipq806x.c
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@@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = {
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static struct pll_freq_tbl pll18_freq_tbl[] = {
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NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
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+ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
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NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
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+ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
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};
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static struct clk_pll pll18 = {
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@@ -2698,7 +2700,7 @@ static struct clk_branch nss_tcm_clk = {
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},
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};
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-static const struct freq_tbl clk_tbl_nss[] = {
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+static const struct freq_tbl clk_tbl_nss_ipq8064[] = {
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{ 110000000, P_PLL18, 1, 1, 5 },
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{ 275000000, P_PLL18, 2, 0, 0 },
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{ 550000000, P_PLL18, 1, 0, 0 },
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@@ -2706,6 +2708,14 @@ static const struct freq_tbl clk_tbl_nss
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{ }
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};
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+static const struct freq_tbl clk_tbl_nss_ipq8065[] = {
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+ { 110000000, P_PLL18, 1, 1, 5 },
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+ { 275000000, P_PLL18, 2, 0, 0 },
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+ { 600000000, P_PLL18, 1, 0, 0 },
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+ { 800000000, P_PLL18, 1, 0, 0 },
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+ { }
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+};
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+
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static struct clk_dyn_rcg ubi32_core1_src_clk = {
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.ns_reg[0] = 0x3d2c,
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.ns_reg[1] = 0x3d30,
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@@ -2745,7 +2755,7 @@ static struct clk_dyn_rcg ubi32_core1_sr
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.pre_div_width = 2,
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},
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.mux_sel_bit = 0,
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- .freq_tbl = clk_tbl_nss,
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+ /* nss freq table is selected based on the SoC compatible */
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.clkr = {
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.enable_reg = 0x3d20,
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.enable_mask = BIT(1),
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@@ -2798,7 +2808,7 @@ static struct clk_dyn_rcg ubi32_core2_sr
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.pre_div_width = 2,
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},
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.mux_sel_bit = 0,
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- .freq_tbl = clk_tbl_nss,
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+ /* nss freq table is selected based on the SoC compatible */
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.clkr = {
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.enable_reg = 0x3d40,
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.enable_mask = BIT(1),
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@@ -3131,6 +3141,14 @@ static int gcc_ipq806x_probe(struct plat
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if (ret)
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return ret;
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+ if (of_machine_is_compatible("qcom,ipq8065")) {
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+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
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+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
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+ } else {
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+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
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+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
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+ }
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+
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ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
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if (ret)
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return ret;
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