5ad826f48a
Replace stmmac pcs fix with upstream version. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
152 lines
5.1 KiB
Diff
152 lines
5.1 KiB
Diff
From 9ec092d2feb69045dd289845024301fb91c064ee Mon Sep 17 00:00:00 2001
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From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
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Date: Tue, 14 Jun 2022 13:22:27 +0200
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Subject: [PATCH 1/2] net: ethernet: stmmac: add missing sgmii configure for
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ipq806x
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The different gmacid require different configuration based on the soc
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and on the gmac id. Add these missing configuration taken from the
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original driver.
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Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
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Link: https://lore.kernel.org/r/20220614112228.1998-1-ansuelsmth@gmail.com
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
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.../ethernet/stmicro/stmmac/dwmac-ipq806x.c | 93 +++++++++++++++----
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2 files changed, 78 insertions(+), 16 deletions(-)
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--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
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+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
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@@ -83,6 +83,7 @@ config DWMAC_IPQ806X
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default ARCH_QCOM
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depends on OF && (ARCH_QCOM || COMPILE_TEST)
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select MFD_SYSCON
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+ select QCOM_SOCINFO
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help
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Support for QCA IPQ806X DWMAC Ethernet.
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
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@@ -27,6 +27,8 @@
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#include <linux/stmmac.h>
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#include <linux/of_mdio.h>
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#include <linux/module.h>
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+#include <linux/sys_soc.h>
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+#include <linux/bitfield.h>
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#include "stmmac_platform.h"
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@@ -75,11 +77,20 @@
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#define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2)
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#define QSGMII_PHY_TX_DRIVER_EN BIT(3)
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#define QSGMII_PHY_QSGMII_EN BIT(7)
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-#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET 12
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-#define QSGMII_PHY_RX_DC_BIAS_OFFSET 18
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-#define QSGMII_PHY_RX_INPUT_EQU_OFFSET 20
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-#define QSGMII_PHY_CDR_PI_SLEW_OFFSET 22
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-#define QSGMII_PHY_TX_DRV_AMP_OFFSET 28
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+#define QSGMII_PHY_DEEMPHASIS_LVL_MASK GENMASK(11, 10)
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+#define QSGMII_PHY_DEEMPHASIS_LVL(x) FIELD_PREP(QSGMII_PHY_DEEMPHASIS_LVL_MASK, (x))
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+#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK GENMASK(14, 12)
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+#define QSGMII_PHY_PHASE_LOOP_GAIN(x) FIELD_PREP(QSGMII_PHY_PHASE_LOOP_GAIN_MASK, (x))
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+#define QSGMII_PHY_RX_DC_BIAS_MASK GENMASK(19, 18)
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+#define QSGMII_PHY_RX_DC_BIAS(x) FIELD_PREP(QSGMII_PHY_RX_DC_BIAS_MASK, (x))
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+#define QSGMII_PHY_RX_INPUT_EQU_MASK GENMASK(21, 20)
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+#define QSGMII_PHY_RX_INPUT_EQU(x) FIELD_PREP(QSGMII_PHY_RX_INPUT_EQU_MASK, (x))
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+#define QSGMII_PHY_CDR_PI_SLEW_MASK GENMASK(23, 22)
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+#define QSGMII_PHY_CDR_PI_SLEW(x) FIELD_PREP(QSGMII_PHY_CDR_PI_SLEW_MASK, (x))
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+#define QSGMII_PHY_TX_SLEW_MASK GENMASK(27, 26)
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+#define QSGMII_PHY_TX_SLEW(x) FIELD_PREP(QSGMII_PHY_TX_SLEW_MASK, (x))
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+#define QSGMII_PHY_TX_DRV_AMP_MASK GENMASK(31, 28)
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+#define QSGMII_PHY_TX_DRV_AMP(x) FIELD_PREP(QSGMII_PHY_TX_DRV_AMP_MASK, (x))
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struct ipq806x_gmac {
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struct platform_device *pdev;
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@@ -242,6 +253,64 @@ static void ipq806x_gmac_fix_mac_speed(v
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ipq806x_gmac_set_speed(gmac, speed);
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}
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+static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = {
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+ {
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+ .revision = "1.*",
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+ },
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+ {
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+ /* sentinel */
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+ }
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+};
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+
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+static int
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+ipq806x_gmac_configure_qsgmii_params(struct ipq806x_gmac *gmac)
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+{
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+ struct platform_device *pdev = gmac->pdev;
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+ const struct soc_device_attribute *soc;
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+ struct device *dev = &pdev->dev;
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+ u32 qsgmii_param;
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+
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+ switch (gmac->id) {
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+ case 1:
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+ soc = soc_device_match(ipq806x_gmac_soc_v1);
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+
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+ if (soc)
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+ qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xc) |
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+ QSGMII_PHY_TX_SLEW(0x2) |
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+ QSGMII_PHY_DEEMPHASIS_LVL(0x2);
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+ else
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+ qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xd) |
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+ QSGMII_PHY_TX_SLEW(0x0) |
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+ QSGMII_PHY_DEEMPHASIS_LVL(0x0);
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+
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+ qsgmii_param |= QSGMII_PHY_RX_DC_BIAS(0x2);
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+ break;
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+ case 2:
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+ case 3:
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+ qsgmii_param = QSGMII_PHY_RX_DC_BIAS(0x3) |
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+ QSGMII_PHY_TX_DRV_AMP(0xc);
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+ break;
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+ default: /* gmac 0 can't be set in SGMII mode */
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+ dev_err(dev, "gmac id %d can't be in SGMII mode", gmac->id);
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+ return -EINVAL;
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+ }
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+
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+ /* Common params across all gmac id */
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+ qsgmii_param |= QSGMII_PHY_CDR_EN |
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+ QSGMII_PHY_RX_FRONT_EN |
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+ QSGMII_PHY_RX_SIGNAL_DETECT_EN |
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+ QSGMII_PHY_TX_DRIVER_EN |
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+ QSGMII_PHY_QSGMII_EN |
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+ QSGMII_PHY_PHASE_LOOP_GAIN(0x4) |
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+ QSGMII_PHY_RX_INPUT_EQU(0x1) |
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+ QSGMII_PHY_CDR_PI_SLEW(0x2);
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+
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+ regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),
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+ qsgmii_param);
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+
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+ return 0;
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+}
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+
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static int ipq806x_gmac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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@@ -328,17 +397,9 @@ static int ipq806x_gmac_probe(struct pla
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regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
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if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) {
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- regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),
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- QSGMII_PHY_CDR_EN |
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- QSGMII_PHY_RX_FRONT_EN |
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- QSGMII_PHY_RX_SIGNAL_DETECT_EN |
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- QSGMII_PHY_TX_DRIVER_EN |
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- QSGMII_PHY_QSGMII_EN |
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- 0x4ul << QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET |
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- 0x3ul << QSGMII_PHY_RX_DC_BIAS_OFFSET |
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- 0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |
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- 0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |
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- 0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);
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+ err = ipq806x_gmac_configure_qsgmii_params(gmac);
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+ if (err)
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+ goto err_remove_config_dt;
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}
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plat_dat->has_gmac = true;
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