1b147bec1a
Refresh ipq806x target patches for kernel 5.15. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
48 lines
1.6 KiB
Diff
48 lines
1.6 KiB
Diff
From 666c1b745e93ccddde841d5057c33f97b29a316a Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 15 Sep 2022 02:19:28 +0200
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Subject: [PATCH 3/9] clk: qcom: krait-cc: handle qsb clock defined in DTS
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qsb fixed clk may be defined in DTS and correctly passed in the clocks
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list. Add related code to handle this and modify the logic to
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dynamically read qsb clock frequency.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/clk/qcom/krait-cc.c | 14 +++++++++++---
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1 file changed, 11 insertions(+), 3 deletions(-)
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--- a/drivers/clk/qcom/krait-cc.c
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+++ b/drivers/clk/qcom/krait-cc.c
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@@ -305,7 +305,7 @@ static int krait_cc_probe(struct platfor
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{
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struct device *dev = &pdev->dev;
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const struct of_device_id *id;
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- unsigned long cur_rate, aux_rate;
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+ unsigned long cur_rate, aux_rate, qsb_rate;
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int cpu;
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struct clk *clk;
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struct clk **clks;
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@@ -315,11 +315,19 @@ static int krait_cc_probe(struct platfor
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if (!id)
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return -ENODEV;
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- /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
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- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
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+ /*
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+ * Per Documentation qsb should be provided from DTS.
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+ * To address old implementation, register the fixed clock anyway.
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+ * Rate is 1 because 0 causes problems for __clk_mux_determine_rate
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+ */
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+ clk = clk_get(dev, "qsb");
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+ if (IS_ERR(clk))
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+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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+ qsb_rate = clk_get_rate(clk);
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+
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if (!id->data) {
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clk = clk_register_fixed_factor(dev, "acpu_aux",
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"gpll0_vote", 0, 1, 2);
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