1b147bec1a
Refresh ipq806x target patches for kernel 5.15. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
98 lines
3.0 KiB
Diff
98 lines
3.0 KiB
Diff
From 6a77cf3f5f95ec0058e1b4d1ada018748cb0b83b Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 15 Sep 2022 03:33:13 +0200
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Subject: [PATCH 9/9] clk: qcom: krait-cc: rework mux reset logic and reset
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hfpll
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Rework and clean mux reset logic.
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Compact it to a for loop to handle both CPU and L2 in one place.
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Move hardcoded aux_rate to define and add a new hfpll_rate value to
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reset hfpll settings.
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Change logic to now reset the hfpll to the lowest value of 600 Mhz and
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then restoring the previous frequency. This permits to reset the hfpll if
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the primary mux was set to source out of the secondary mux.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/clk/qcom/krait-cc.c | 50 +++++++++++++++++--------------------
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1 file changed, 23 insertions(+), 27 deletions(-)
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--- a/drivers/clk/qcom/krait-cc.c
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+++ b/drivers/clk/qcom/krait-cc.c
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@@ -15,7 +15,9 @@
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#include "clk-krait.h"
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-#define QSB_RATE 2250000000
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+#define QSB_RATE 225000000
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+#define AUX_RATE 384000000
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+#define HFPLL_RATE 600000000
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static unsigned int sec_mux_map[] = {
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2,
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@@ -317,7 +319,7 @@ static int krait_cc_probe(struct platfor
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{
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struct device *dev = &pdev->dev;
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const struct of_device_id *id;
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- unsigned long cur_rate, aux_rate, qsb_rate, pxo_rate;
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+ unsigned long cur_rate, qsb_rate, pxo_rate;
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int cpu;
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struct clk *clk;
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struct clk **clks;
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@@ -397,36 +399,30 @@ static int krait_cc_probe(struct platfor
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* two different rates to force a HFPLL reinit under all
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* circumstances.
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*/
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- cur_rate = clk_get_rate(l2_pri_mux_clk);
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- aux_rate = 384000000;
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- if (cur_rate == qsb_rate) {
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- dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n");
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- cur_rate = aux_rate;
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- }
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- if (cur_rate == pxo_rate) {
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- dev_info(dev, "L2 @ PXO rate. Forcing new rate.\n");
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- cur_rate = aux_rate;
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- }
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- clk_set_rate(l2_pri_mux_clk, aux_rate);
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- clk_set_rate(l2_pri_mux_clk, 2);
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- clk_set_rate(l2_pri_mux_clk, cur_rate);
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- dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
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- for_each_possible_cpu(cpu) {
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+ for (cpu = 0; cpu < 5; cpu++) {
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+ const char *l2_s = "L2";
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+ char cpu_s[5];
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+
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clk = clks[cpu];
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+ if (!clk)
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+ continue;
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+
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+ if (cpu < 4)
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+ snprintf(cpu_s, 5, "CPU%d", cpu);
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+
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cur_rate = clk_get_rate(clk);
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- if (cur_rate == qsb_rate) {
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- dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu);
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- cur_rate = aux_rate;
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- }
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- if (cur_rate ==pxo_rate) {
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- dev_info(dev, "CPU%d @ PXO rate. Forcing new rate.\n", cpu);
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- cur_rate = aux_rate;
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+ if (cur_rate == qsb_rate || cur_rate == pxo_rate) {
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+ dev_info(dev, "%s @ %s rate. Forcing new rate.\n",
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+ cpu < 4 ? cpu_s : l2_s,
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+ cur_rate == qsb_rate ? "QSB" : "PXO");
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+ cur_rate = AUX_RATE;
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}
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- clk_set_rate(clk, aux_rate);
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- clk_set_rate(clk, 2);
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+ clk_set_rate(clk, AUX_RATE);
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+ clk_set_rate(clk, HFPLL_RATE);
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clk_set_rate(clk, cur_rate);
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- dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
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+ dev_info(dev, "%s @ %lu KHz\n", cpu < 4 ? cpu_s : l2_s,
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+ clk_get_rate(clk) / 1000);
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}
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of_clk_add_provider(dev->of_node, krait_of_get, clks);
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