863e79f8d5
The following patches were dropped because they are already applied upstream: 0012-pinctrl-lantiq-fix-up-pinmux.patch 0013-MTD-lantiq-xway-fix-invalid-operator.patch 0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch 0015-MTD-lantiq-xway-remove-endless-loop.patch 0016-MTD-lantiq-xway-add-missing-write_buf-and-read_buf-t.patch 0017-MTD-xway-fix-nand-locking.patch 0044-pinctrl-lantiq-introduce-new-dedicated-devicetree-bi.patch 0045-pinctrl-lantiq-Fix-GPIO-Setup-of-GPIO-Port3.patch 0046-pinctrl-lantiq-2-pins-have-the-wrong-mux-list.patch 0047-irq-fixes.patch 0047-mtd-plat-nand-pass-of-node.patch 0060-usb-dwc2-Add-support-for-Lantiq-ARX-and-XRX-SoCs.patch 0120-MIPS-lantiq-add-support-for-device-tree-file-from-bo.patch 0121-MIPS-lantiq-make-it-possible-to-build-in-no-device-t.patch 122-MIPS-store-the-appended-dtb-address-in-a-variable.patch The PHY driver was reduced to the code adding the LED configuration, the rest is already upstream: 0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch The SPI driver was replaced with the version pending for upstream inclusion: New driver: 0090-spi-add-transfer_status-callback.patch 0091-spi-lantiq-ssc-add-support-for-Lantiq-SSC-SPI-controller.patch Old driver: 0100-spi-add-support-for-Lantiq-SPI-controller.patch Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
31 lines
731 B
Diff
31 lines
731 B
Diff
--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -442,6 +442,20 @@ static void clkdev_add_clkout(void)
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}
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}
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+static void set_phy_clock_source(struct device_node *np_cgu)
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+{
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+ u32 phy_clk_src, ifcc;
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+
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+ if (!np_cgu)
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+ return;
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+
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+ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
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+ return;
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+
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+ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
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+ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
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+}
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+
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/* bring up all register ranges that we need for basic system control */
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void __init ltq_soc_init(void)
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{
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@@ -628,4 +642,6 @@ void __init ltq_soc_init(void)
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if (of_machine_is_compatible("lantiq,vr9"))
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xbar_fpi_burst_disable();
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usb_set_clock();
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+
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+ set_phy_clock_source(np_cgu);
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}
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