1343acc8cd
Deleted (upstreamed): bcm27xx/patches-5.10/950-0669-drm-vc4-hdmi-Make-sure-the-device-is-powered-with-CE.patch [1] bcm27xx/patches-5.10/950-0672-drm-vc4-hdmi-Move-initial-register-read-after-pm_run.patch [1] gemini/patches-5.10/0003-ARM-dts-gemini-NAS4220-B-fis-index-block-with-128-Ki.patch [2] Manually rebased: bcm27xx/patches-5.10/950-0675-drm-vc4-hdmi-Drop-devm-interrupt-handler-for-CEC-int.patch Manually reverted: generic/pending-5.10/860-Revert-ASoC-mediatek-Check-for-error-clk-pointer.patch [3] [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.94&id=55b10b88ac8654fc2f31518aa349a2e643b37f18 [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.94&id=958a8819d41420d7a74ed922a09cacc0ba3a4218 [3] https://lore.kernel.org/all/trinity-2a727d96-0335-4d03-8f30-e22a0e10112d-1643363480085@3c-app-gmx-bap33/ Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
74 lines
2.1 KiB
Diff
74 lines
2.1 KiB
Diff
From 8ea673a8b30b4a32516b8adabb15e2a68ff02ec8 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Tue, 30 Nov 2021 18:29:04 +0100
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Subject: [PATCH] PCI: pci-bridge-emul: Add definitions for missing
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capabilities registers
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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pci-bridge-emul driver already allocates buffer for capabilities up to the
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PCI_EXP_SLTSTA2 register, but does not define bit access behavior for these
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registers. Add these missing definitions.
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Link: https://lore.kernel.org/r/20211130172913.9727-3-kabel@kernel.org
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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---
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drivers/pci/pci-bridge-emul.c | 43 +++++++++++++++++++++++++++++++++++
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1 file changed, 43 insertions(+)
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--- a/drivers/pci/pci-bridge-emul.c
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+++ b/drivers/pci/pci-bridge-emul.c
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@@ -270,6 +270,49 @@ struct pci_bridge_reg_behavior pcie_cap_
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.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
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.w1c = PCI_EXP_RTSTA_PME,
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},
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+
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+ [PCI_EXP_DEVCAP2 / 4] = {
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+ /*
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+ * Device capabilities 2 register has reserved bits [30:27].
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+ * Also bits [26:24] are reserved for non-upstream ports.
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+ */
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+ .ro = BIT(31) | GENMASK(23, 0),
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+ },
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+
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+ [PCI_EXP_DEVCTL2 / 4] = {
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+ /*
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+ * Device control 2 register is RW. Bit 11 is reserved for
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+ * non-upstream ports.
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+ *
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+ * Device status 2 register is reserved.
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+ */
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+ .rw = GENMASK(15, 12) | GENMASK(10, 0),
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+ },
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+
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+ [PCI_EXP_LNKCAP2 / 4] = {
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+ /* Link capabilities 2 register has reserved bits [30:25] and 0. */
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+ .ro = BIT(31) | GENMASK(24, 1),
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+ },
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+
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+ [PCI_EXP_LNKCTL2 / 4] = {
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+ /*
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+ * Link control 2 register is RW.
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+ *
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+ * Link status 2 register has bits 5, 15 W1C;
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+ * bits 10, 11 reserved and others are RO.
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+ */
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+ .rw = GENMASK(15, 0),
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+ .w1c = (BIT(15) | BIT(5)) << 16,
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+ .ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
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+ },
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+
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+ [PCI_EXP_SLTCAP2 / 4] = {
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+ /* Slot capabilities 2 register is reserved. */
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+ },
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+
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+ [PCI_EXP_SLTCTL2 / 4] = {
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+ /* Both Slot control 2 and Slot status 2 registers are reserved. */
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+ },
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};
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/*
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