af6cd37f42
Patches to support the SoC's GPIO controller for RTL930x and RTL931x devices have been accepted upstream. Replace the current preliminary patch with the upstream ones, excluding devictree binding changes. The updated patches add GPIO IRQ balancing support on RTL930x, but this cannot be used until these devices also support SMP. Signed-off-by: Sander Vanheule <sander@svanheule.net>
124 lines
4.2 KiB
Diff
124 lines
4.2 KiB
Diff
From 512c5be35223d9baa2629efa1084cf5210eaee80 Mon Sep 17 00:00:00 2001
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From: Sander Vanheule <sander@svanheule.net>
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Date: Sat, 9 Apr 2022 21:55:47 +0200
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Subject: [PATCH 2/6] gpio: realtek-otto: Support reversed port layouts
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The GPIO port layout on the RTL930x SoC series is reversed compared to
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the RTL838x and RTL839x SoC series. Add new port offset calculator
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functions to ensure the correct order is used when reading port IRQ
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data, and ensure bgpio uses the right byte ordering.
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Signed-off-by: Sander Vanheule <sander@svanheule.net>
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Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
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---
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drivers/gpio/gpio-realtek-otto.c | 55 +++++++++++++++++++++++++++++---
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1 file changed, 51 insertions(+), 4 deletions(-)
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--- a/drivers/gpio/gpio-realtek-otto.c
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+++ b/drivers/gpio/gpio-realtek-otto.c
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@@ -58,6 +58,8 @@ struct realtek_gpio_ctrl {
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raw_spinlock_t lock;
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u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK];
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u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK];
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+ unsigned int (*port_offset_u8)(unsigned int port);
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+ unsigned int (*port_offset_u16)(unsigned int port);
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};
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/* Expand with more flags as devices with other quirks are added */
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@@ -69,6 +71,11 @@ enum realtek_gpio_flags {
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* line the IRQ handler was assigned to, causing uncaught interrupts.
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*/
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GPIO_INTERRUPTS_DISABLED = BIT(0),
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+ /*
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+ * Port order is reversed, meaning DCBA register layout for 1-bit
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+ * fields, and [BA, DC] for 2-bit fields.
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+ */
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+ GPIO_PORTS_REVERSED = BIT(1),
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};
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static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)
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@@ -86,21 +93,50 @@ static struct realtek_gpio_ctrl *irq_dat
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* port. The two interrupt mask registers store two bits per GPIO, so use u16
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* values.
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*/
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+static unsigned int realtek_gpio_port_offset_u8(unsigned int port)
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+{
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+ return port;
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+}
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+
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+static unsigned int realtek_gpio_port_offset_u16(unsigned int port)
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+{
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+ return 2 * port;
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+}
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+
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+/*
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+ * Reversed port order register access
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+ *
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+ * For registers with one bit per GPIO, all ports are stored as u8-s in one
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+ * register in reversed order. The two interrupt mask registers store two bits
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+ * per GPIO, so use u16 values. The first register contains ports 1 and 0, the
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+ * second ports 3 and 2.
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+ */
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+static unsigned int realtek_gpio_port_offset_u8_rev(unsigned int port)
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+{
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+ return 3 - port;
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+}
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+
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+static unsigned int realtek_gpio_port_offset_u16_rev(unsigned int port)
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+{
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+ return 2 * (port ^ 1);
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+}
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+
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static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl,
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unsigned int port, u16 irq_type, u16 irq_mask)
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{
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- iowrite16(irq_type & irq_mask, ctrl->base + REALTEK_GPIO_REG_IMR + 2 * port);
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+ iowrite16(irq_type & irq_mask,
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+ ctrl->base + REALTEK_GPIO_REG_IMR + ctrl->port_offset_u16(port));
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}
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static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl,
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unsigned int port, u8 mask)
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{
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- iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + port);
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+ iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port));
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}
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static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port)
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{
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- return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + port);
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+ return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port));
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}
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/* Set the rising and falling edge mask bits for a GPIO port pin */
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@@ -253,6 +289,7 @@ MODULE_DEVICE_TABLE(of, realtek_gpio_of_
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static int realtek_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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+ unsigned long bgpio_flags;
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unsigned int dev_flags;
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struct gpio_irq_chip *girq;
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struct realtek_gpio_ctrl *ctrl;
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@@ -280,10 +317,20 @@ static int realtek_gpio_probe(struct pla
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raw_spin_lock_init(&ctrl->lock);
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+ if (dev_flags & GPIO_PORTS_REVERSED) {
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+ bgpio_flags = 0;
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+ ctrl->port_offset_u8 = realtek_gpio_port_offset_u8_rev;
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+ ctrl->port_offset_u16 = realtek_gpio_port_offset_u16_rev;
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+ } else {
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+ bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
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+ ctrl->port_offset_u8 = realtek_gpio_port_offset_u8;
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+ ctrl->port_offset_u16 = realtek_gpio_port_offset_u16;
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+ }
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+
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err = bgpio_init(&ctrl->gc, dev, 4,
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ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL,
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ctrl->base + REALTEK_GPIO_REG_DIR, NULL,
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- BGPIOF_BIG_ENDIAN_BYTE_ORDER);
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+ bgpio_flags);
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if (err) {
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dev_err(dev, "unable to init generic GPIO");
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return err;
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