tn3399_openwrt/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts
Adrian Schmutzler 3a4b751110 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-02-24 02:53:53 +01:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca955x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Sitecom WLR-8100 (X8 AC1750)";
compatible = "sitecom,wlr-8100", "qca,qca9558";
aliases {
led-boot = &led_status_amber;
led-failsafe = &led_status_amber;
led-running = &led_status_amber;
led-upgrade = &led_status_amber;
};
keys {
compatible = "gpio-keys";
wifi2g_rfkill {
label = "2.4GHz - RFKILL";
gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
wifi5g_restart {
label = "5GHz - RESTART";
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_status_amber: status_amber {
label = "amber:status";
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
default-state = "on";
};
ops {
label = "white:ops";
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
};
wifi2g {
label = "blue:wifi2g";
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
wifi5g {
label = "blue:wifi5g";
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
};
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
uboot: partition@0 {
label = "u-boot";
reg = <0x000000 0x030000>;
read-only;
};
partition@30000 {
label = "u-boot-env";
reg = <0x030000 0x010000>;
read-only;
};
partition@40000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x040000 0xf10000>;
};
partition@f50000 {
label = "manufacture";
reg = <0xf50000 0x040000>;
read-only;
};
partition@f90000 {
label = "backup";
reg = <0xf90000 0x010000>;
read-only;
};
partition@fa0000 {
label = "storage";
reg = <0xfa0000 0x050000>;
read-only;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0 0 0 0 0>;
};
};
&usb_phy0 {
status = "okay";
};
&usb0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
&mdio0 {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x04 0x87600000 /* PORT0 PAD MODE CTRL */
0x50 0xcf37cf37 /* LED Control Register 0 */
0x54 0x00000000 /* LED Control Register 1 */
0x58 0x00000000 /* LED Control Register 2 */
0x5c 0x0030c300 /* LED Control Register 3 */
0x7c 0x0000007e /* PORT0_STATUS */
>;
};
};
&eth0 {
status = "okay";
phy-handle = <&phy0>;
pll-data = <0xa6000000 0x00000101 0x00001616>;
gmac-config {
device = <&gmac>;
rgmii-enabled = <1>;
};
};
&wmac {
status = "okay";
qca,no-eeprom;
};