88bf652525
Reorganize dtsi patches with upstream version and drop dtsi in 5.15 files. Also add an additional upstream patch for hwspinlock support. Refresh all the dts with needed changes. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
130 lines
2.8 KiB
Diff
130 lines
2.8 KiB
Diff
From 9f7097a8b1948533a6db1b53b5c0480cc75bbd16 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Mon, 18 Jul 2022 18:05:16 +0200
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Subject: [PATCH 1/3] ARM: dts: qcom: ipq8064: add v2 dtsi variant
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Add ipq8064-v2.0 dtsi variant that differ from original ipq8064 SoC for
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some additional pcie, sata and usb configuration values, additional
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reserved memory and serial output.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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.../boot/dts/qcom-ipq8064-v2.0-smb208.dtsi | 37 ++++++++++
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arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 +++++++++++++++++++
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2 files changed, 106 insertions(+)
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create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
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create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
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@@ -0,0 +1,37 @@
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+// SPDX-License-Identifier: GPL-2.0
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+
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+#include "qcom-ipq8064-v2.0.dtsi"
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+
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+&rpm {
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+ smb208_regulators: regulators {
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+ compatible = "qcom,rpm-smb208-regulators";
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+
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+ smb208_s1a: s1a {
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+ regulator-min-microvolt = <1050000>;
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+ regulator-max-microvolt = <1150000>;
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+
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+ qcom,switch-mode-frequency = <1200000>;
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+ };
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+
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+ smb208_s1b: s1b {
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+ regulator-min-microvolt = <1050000>;
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+ regulator-max-microvolt = <1150000>;
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+
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+ qcom,switch-mode-frequency = <1200000>;
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+ };
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+
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+ smb208_s2a: s2a {
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+ regulator-min-microvolt = < 800000>;
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+ regulator-max-microvolt = <1250000>;
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+
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+ qcom,switch-mode-frequency = <1200000>;
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+ };
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+
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+ smb208_s2b: s2b {
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+ regulator-min-microvolt = < 800000>;
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+ regulator-max-microvolt = <1250000>;
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+
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+ qcom,switch-mode-frequency = <1200000>;
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
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@@ -0,0 +1,69 @@
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+// SPDX-License-Identifier: GPL-2.0
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+
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+#include "qcom-ipq8064.dtsi"
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+
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+/ {
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+ model = "Qualcomm Technologies, Inc. IPQ8064-v2.0";
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+
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+ aliases {
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+ serial0 = &gsbi4_serial;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ reserved-memory {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ rsvd@41200000 {
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+ reg = <0x41200000 0x300000>;
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+ no-map;
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+ };
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+ };
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+};
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+
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+&gsbi4 {
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+ qcom,mode = <GSBI_PROT_I2C_UART>;
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+ status = "okay";
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+
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+ serial@16340000 {
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+ status = "okay";
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+ };
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+ /*
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+ * The i2c device on gsbi4 should not be enabled.
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+ * On ipq806x designs gsbi4 i2c is meant for exclusive
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+ * RPM usage. Turning this on in kernel manifests as
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+ * i2c failure for the RPM.
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+ */
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+};
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+
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+&pcie0 {
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+ compatible = "qcom,pcie-ipq8064-v2";
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+};
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+
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+&pcie1 {
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+ compatible = "qcom,pcie-ipq8064-v2";
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+};
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+
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+&pcie2 {
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+ compatible = "qcom,pcie-ipq8064-v2";
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+};
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+
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+&sata {
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+ ports-implemented = <0x1>;
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+};
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+
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+&ss_phy_0 {
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+ qcom,rx-eq = <2>;
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+ qcom,tx-deamp_3_5db = <32>;
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+ qcom,mpll = <5>;
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+};
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+
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+&ss_phy_1 {
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+ qcom,rx-eq = <2>;
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+ qcom,tx-deamp_3_5db = <32>;
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+ qcom,mpll = <5>;
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+};
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