9a038e7fd1
Copy config and patches from kernel 5.10 to kernel 5.15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
31 lines
1.0 KiB
Diff
31 lines
1.0 KiB
Diff
From 245224608b5368c10407da07557e546743d3c489 Mon Sep 17 00:00:00 2001
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From: Nick Hainke <vincent@systemli.org>
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Date: Mon, 27 Dec 2021 09:33:13 +0100
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Subject: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
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Macronix flash chips seem to consist of only one status register.
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These chips will not work with the "16-bit Write Status (01h) Command".
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Disable SNOR_F_HAS_16BIT_SR for all Macronix chips.
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Tested with MX25L6405D.
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Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
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lock()/unlock()")
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Signed-off-by: David Bauer <mail@david-bauer.net>
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Signed-off-by: Nick Hainke <vincent@systemli.org>
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---
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drivers/mtd/spi-nor/macronix.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/drivers/mtd/spi-nor/macronix.c
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+++ b/drivers/mtd/spi-nor/macronix.c
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@@ -94,6 +94,7 @@ static void macronix_default_init(struct
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{
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nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
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nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
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+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
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nor->flags |= SNOR_F_HAS_LOCK;
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}
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