f2f42a54e8
The qca8k patch series brings the numbering to 799. This patch renames 7xx patches to create space for more backports to be added. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> [rename 729->719] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
48 lines
1.5 KiB
Diff
48 lines
1.5 KiB
Diff
From 9fe99de01440d9ede74d447ac76e9c445d8daae9 Mon Sep 17 00:00:00 2001
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From: Yang Yingliang <yangyingliang@huawei.com>
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Date: Sat, 29 May 2021 11:04:39 +0800
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Subject: [PATCH] net: dsa: qca8k: add missing check return value in
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qca8k_phylink_mac_config()
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Now we can check qca8k_read() return value correctly, so if
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it fails, we need return directly.
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Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/dsa/qca8k.c | 9 +++++++--
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1 file changed, 7 insertions(+), 2 deletions(-)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -1128,6 +1128,7 @@ qca8k_phylink_mac_config(struct dsa_swit
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{
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struct qca8k_priv *priv = ds->priv;
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u32 reg, val;
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+ int ret;
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switch (port) {
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case 0: /* 1st CPU port */
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@@ -1198,7 +1199,9 @@ qca8k_phylink_mac_config(struct dsa_swit
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qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
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/* Enable/disable SerDes auto-negotiation as necessary */
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- qca8k_read(priv, QCA8K_REG_PWS, &val);
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+ ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
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+ if (ret)
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+ return;
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if (phylink_autoneg_inband(mode))
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val &= ~QCA8K_PWS_SERDES_AEN_DIS;
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else
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@@ -1206,7 +1209,9 @@ qca8k_phylink_mac_config(struct dsa_swit
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qca8k_write(priv, QCA8K_REG_PWS, val);
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/* Configure the SGMII parameters */
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- qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
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+ ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
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+ if (ret)
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+ return;
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val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
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QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
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