166 lines
3.3 KiB
Diff
166 lines
3.3 KiB
Diff
From 9ee7fd7aa956671727752dac6bd131cf511c1137 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Thu, 15 Apr 2021 13:49:59 +0300
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Subject: [PATCH 209/247] ARM: at91: pm: add support for MCK1..4 save/restore
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for ulp modes
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Add support for MCK1..4 save restore for ULP modes.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Link: https://lore.kernel.org/r/20210415105010.569620-14-claudiu.beznea@microchip.com
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---
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arch/arm/mach-at91/pm_suspend.S | 126 ++++++++++++++++++++++++++++++++
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1 file changed, 126 insertions(+)
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--- a/arch/arm/mach-at91/pm_suspend.S
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+++ b/arch/arm/mach-at91/pm_suspend.S
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@@ -765,7 +765,122 @@ sr_dis_exit:
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2:
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.endm
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+/**
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+ * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock
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+ *
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+ * Side effects: overwrites tmp1, tmp2
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+ */
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+.macro at91_mckx_ps_enable
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+#ifdef CONFIG_SOC_SAMA7
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+ ldr pmc, .pmc_base
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+
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+ /* There are 4 MCKs we need to handle: MCK1..4 */
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+ mov tmp1, #1
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+e_loop: cmp tmp1, #5
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+ beq e_done
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+
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+ /* Write MCK ID to retrieve the settings. */
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+ str tmp1, [pmc, #AT91_PMC_MCR_V2]
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+ ldr tmp2, [pmc, #AT91_PMC_MCR_V2]
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+
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+e_save_mck1:
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+ cmp tmp1, #1
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+ bne e_save_mck2
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+ str tmp2, .saved_mck1
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+ b e_ps
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+
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+e_save_mck2:
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+ cmp tmp1, #2
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+ bne e_save_mck3
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+ str tmp2, .saved_mck2
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+ b e_ps
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+
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+e_save_mck3:
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+ cmp tmp1, #3
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+ bne e_save_mck4
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+ str tmp2, .saved_mck3
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+ b e_ps
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+
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+e_save_mck4:
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+ str tmp2, .saved_mck4
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+
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+e_ps:
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+ /* Use CSS=MAINCK and DIV=1. */
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+ bic tmp2, tmp2, #AT91_PMC_MCR_V2_CSS
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+ bic tmp2, tmp2, #AT91_PMC_MCR_V2_DIV
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+ orr tmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK
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+ orr tmp2, tmp2, #AT91_PMC_MCR_V2_DIV1
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+ str tmp2, [pmc, #AT91_PMC_MCR_V2]
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+
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+ wait_mckrdy tmp1
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+
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+ add tmp1, tmp1, #1
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+ b e_loop
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+
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+e_done:
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+#endif
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+.endm
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+
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+/**
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+ * at91_mckx_ps_restore: restore MCK1..4 settings
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+ *
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+ * Side effects: overwrites tmp1, tmp2
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+ */
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+.macro at91_mckx_ps_restore
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+#ifdef CONFIG_SOC_SAMA7
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+ ldr pmc, .pmc_base
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+
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+ /* There are 4 MCKs we need to handle: MCK1..4 */
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+ mov tmp1, #1
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+r_loop: cmp tmp1, #5
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+ beq r_done
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+
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+r_save_mck1:
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+ cmp tmp1, #1
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+ bne r_save_mck2
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+ ldr tmp2, .saved_mck1
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+ b r_ps
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+
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+r_save_mck2:
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+ cmp tmp1, #2
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+ bne r_save_mck3
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+ ldr tmp2, .saved_mck2
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+ b r_ps
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+
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+r_save_mck3:
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+ cmp tmp1, #3
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+ bne r_save_mck4
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+ ldr tmp2, .saved_mck3
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+ b r_ps
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+
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+r_save_mck4:
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+ ldr tmp2, .saved_mck4
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+
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+r_ps:
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+ /* Write MCK ID to retrieve the settings. */
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+ str tmp1, [pmc, #AT91_PMC_MCR_V2]
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+ ldr tmp3, [pmc, #AT91_PMC_MCR_V2]
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+
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+ /* We need to restore CSS and DIV. */
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+ bic tmp3, tmp3, #AT91_PMC_MCR_V2_CSS
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+ bic tmp3, tmp3, #AT91_PMC_MCR_V2_DIV
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+ orr tmp3, tmp3, tmp2
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+ bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK
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+ orr tmp3, tmp3, tmp1
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+ orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD
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+ str tmp2, [pmc, #AT91_PMC_MCR_V2]
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+
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+ wait_mckrdy tmp1
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+
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+ add tmp1, tmp1, #1
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+ b r_loop
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+r_done:
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+#endif
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+.endm
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+
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.macro at91_ulp_mode
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+ at91_mckx_ps_enable
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+
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ldr pmc, .pmc_base
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ldr tmp2, .mckr_offset
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ldr tmp3, .pm_mode
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@@ -817,6 +932,7 @@ ulp_exit:
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mov tmp3, #0
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wait_mckrdy tmp3
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+ at91_mckx_ps_restore
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.endm
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.macro at91_backup_mode
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@@ -946,6 +1062,16 @@ ENDPROC(at91_pm_suspend_in_sram)
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.word 0
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.saved_osc_status:
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.word 0
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+#ifdef CONFIG_SOC_SAMA7
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+.saved_mck1:
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+ .word 0
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+.saved_mck2:
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+ .word 0
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+.saved_mck3:
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+ .word 0
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+.saved_mck4:
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+ .word 0
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+#endif
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ENTRY(at91_pm_suspend_in_sram_sz)
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.word .-at91_pm_suspend_in_sram
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