88bf652525
Reorganize dtsi patches with upstream version and drop dtsi in 5.15 files. Also add an additional upstream patch for hwspinlock support. Refresh all the dts with needed changes. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
95 lines
2.5 KiB
Diff
95 lines
2.5 KiB
Diff
From 6c421a9c08286389bb331fe783e2625c9efcc187 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 7 Jul 2022 03:09:41 +0200
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Subject: [PATCH 7/8] ARM: dts: qcom: ipq8064: fix and add some missing gsbi
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node
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Add some tag for gsbi to make them usable for ipq8064 SoC. Add missing
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gsbi7 i2c node and gsbi1 node.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Tested-by: Jonathan McDowell <noodles@earth.li>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220707010943.20857-8-ansuelsmth@gmail.com
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---
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 54 ++++++++++++++++++++++++++++-
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1 file changed, 53 insertions(+), 1 deletion(-)
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -539,6 +539,44 @@
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regulator;
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};
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+ gsbi1: gsbi@12440000 {
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+ compatible = "qcom,gsbi-v1.0.0";
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+ reg = <0x12440000 0x100>;
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+ cell-index = <1>;
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+ clocks = <&gcc GSBI1_H_CLK>;
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+ clock-names = "iface";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ syscon-tcsr = <&tcsr>;
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+
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+ status = "disabled";
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+
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+ gsbi1_serial: serial@12450000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x12450000 0x100>,
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+ <0x12400000 0x03>;
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+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
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+ clock-names = "core", "iface";
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+
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+ status = "disabled";
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+ };
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+
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+ gsbi1_i2c: i2c@12460000 {
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+ compatible = "qcom,i2c-qup-v1.1.1";
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+ reg = <0x12460000 0x1000>;
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+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
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+ clock-names = "core", "iface";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ status = "disabled";
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+ };
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+ };
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+
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gsbi2: gsbi@12480000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <2>;
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@@ -562,7 +600,7 @@
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status = "disabled";
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};
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- i2c@124a0000 {
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+ gsbi2_i2c: i2c@124a0000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x124a0000 0x1000>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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@@ -727,6 +765,20 @@
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clock-names = "core", "iface";
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status = "disabled";
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};
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+
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+ gsbi7_i2c: i2c@16680000 {
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+ compatible = "qcom,i2c-qup-v1.1.1";
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+ reg = <0x16680000 0x1000>;
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+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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+
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+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
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+ clock-names = "core", "iface";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ status = "disabled";
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+ };
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};
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rng@1a500000 {
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