2ee98e8f6e
This should align opp table with what it was before converting to OPP v2. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com> Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
33 lines
1.2 KiB
Diff
33 lines
1.2 KiB
Diff
From: Niklas Cassel <niklas.cassel@linaro.org>
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Subject: [PATCH] ARM: dts: qcom: ipq4019: Fix MSI IRQ type
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Date: Thu, 24 Jan 2019 14:00:47 +0100
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The databook clearly states that the MSI IRQ (msi_ctrl_int) is a level
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triggered interrupt.
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The msi_ctrl_int will be high for as long as any MSI status bit is set,
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thus the IRQ type should be set to IRQ_TYPE_LEVEL_HIGH, causing the
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IRQ handler to keep getting called, as long as any MSI status bit is set.
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A git grep shows that ipq4019 is the only SoC using snps,dw-pcie that has
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configured this IRQ incorrectly.
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Not having the correct IRQ type defined will cause us to lose interrupts,
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which in turn causes timeouts in the PCIe endpoint drivers.
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Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
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Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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---
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -404,7 +404,7 @@
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ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
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<0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
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- interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
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+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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