9b90dc05f5
This patch is based on #1689 and adds support for TP-Link Archer C6 v2 (US) and A6 (US/TW). The hardware is the same as EU and RU variant, except for GPIOs (LEDS/Buttons), flash(chip/partitions) and UART being available on the board. - SOC: Qualcomm QCA9563 @ 775MHz - Flash: GigaDevice GD25Q127CS1G (16MiB) - RAM: Zentel A3R1GE40JBF (128 MiB DDR2) - Ethernet: Qualcomm QCA8337N: 4x 1Gbps LAN + 1x 1Gbps WAN - Wireless: - 2.4GHz (bgn) QCA9563 integrated (3x3) - 5GHz (ac) Qualcomm QCA9886 (2x2) - Button: 1x power, 1x reset, 1x wps - LED: 6x LEDs: power, wlan2g, wlan5g, lan, wan, wps - UART: 115200, 8n1 (header available on board) Known issues: - Wireless: 5GHz is known to have lower RSSI signal, it affects speed and range. Flash instructions: Upload openwrt-ath79-generic-tplink_archer-c6-v2-us-squashfs-factory.bin via the router Web interface. Flash instruction using tftp recovery: 1. Connect the computer to one of the LAN ports of the router 2. Set the computer IP to 192.168.0.66 3. Start a tftp server with the OpenWrt factory image in the tftp root directory renamed to ArcherA6v2_tp_recovery.bin. 4. Connect power cable to router, press and hold the reset button and turn the router on 5. Keep the reset button pressed until the WPS LED lights up 6. Wait ~150 seconds to complete flashing Flash partitioning: I've followed #1689 for defining the partition layout for this patch. The partition named as "tplink" @ 0xfd0000 is marked as read only as it is where some config for stock firmware are stored. On stock firmware those stock partitions starts at 0xfd9400 however I had not been able to make it functional starting on the same address as on stock fw, so it has been partitioned following #1689 and not the stock partition layout for this specific partition. Due to that firmware/rootfs partition lenght is 0xf80000 and not 0xf89400 as stock. According to the GPL code, the EU/RU/JP variant does have different GPIO pins assignment to LEDs and buttons, also the flash memory layout is different. GPL Source Code: https://static.tp-link.com/resources/gpl/gpl-A6v2_us.tar.gz Signed-off-by: Anderson Vulczak <andi@andi.com.br> [wrap commit message, remove soft_ver change for C6 v2 EU, move LED aliases to DTS files, remove dts-v1 in DTSI, node/property reorder in DTSI] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
131 lines
2.2 KiB
Plaintext
131 lines
2.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include "qca9563_tplink_archer-x6-v2.dtsi"
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/ {
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compatible = "tplink,archer-c6-v2-us", "qca,qca9563";
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model = "TP-Link Archer C6 v2 (US) / A6 v2 (US/TW)";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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leds {
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compatible = "gpio-leds";
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led_power: power {
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label = "tp-link:green:power";
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gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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wlan2g {
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label = "tp-link:green:wlan2g";
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gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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wlan5g {
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label = "tp-link:green:wlan5g";
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gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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lan {
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label = "tp-link:green:lan";
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gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
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};
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wan {
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label = "tp-link:green:wan";
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gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
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};
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wan_fail {
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label = "tp-link:amber:wan";
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gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
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};
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wps {
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label = "tp-link:green:wps";
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gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "Reset button";
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linux,code = <KEY_RESTART>;
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gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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wps {
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label = "WPS button";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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};
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};
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&spi {
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status = "okay";
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num-cs = <1>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <25000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "factory-boot";
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reg = <0x000000 0x020000>;
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read-only;
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};
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mac: partition@20000 {
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label = "mac";
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reg = <0x020000 0x010000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot";
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reg = <0x030000 0x020000>;
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read-only;
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};
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partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x050000 0xf80000>;
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};
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partition@fd0000 {
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label = "tplink";
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reg = <0xfd0000 0x020000>;
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read-only;
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};
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art: partition@ff0000 {
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label = "art";
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reg = <0xff0000 0x010000>;
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read-only;
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};
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};
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};
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};
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