69df7eb73d
Currently AR724x pinmux for register 0x18040028 controls only JTAG disable bit. This patch adds new DTS settings to control LAN LEDs and CLKs that allow full software control over these diodes - exactly the same is done by ar71xx target in device setup phase for many routers (WNR2000v3 for example). 'switch_led_disable_pins' clears AR724X_GPIO_FUNC_ETH_SWITCH_LED[0-4]_EN bits. 'clks_disable_pins' clears AR724X_GPIO_FUNC_CLK_OBS[1-5]_EN and AR724X_GPIO_FUNC_GE0_MII_CLK_EN bits. These all should be used together, along with 'jtag_disable_pins', to allow OS to control all GPIO-connected LEDs and buttons on device. Signed-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>
163 lines
3.4 KiB
Plaintext
163 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/clock/ath79-clk.h>
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#include "ath79.dtsi"
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/ {
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compatible = "qca,ar7240";
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "mips,mips24Kc";
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clocks = <&pll ATH79_CLK_CPU>;
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reg = <0>;
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};
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};
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ahb: ahb {
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apb {
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ddr_ctrl: memory-controller@18000000 {
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compatible = "qca,ar9132-ddr-controller",
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"qca,ar7240-ddr-controller";
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reg = <0x18000000 0x100>;
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#qca,ddr-wb-channel-cells = <1>;
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};
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uart: uart@18020000 {
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compatible = "ns16550a";
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reg = <0x18020000 0x20>;
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interrupts = <3>;
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clocks = <&pll ATH79_CLK_AHB>;
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clock-names = "uart";
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reg-io-width = <4>;
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reg-shift = <2>;
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no-loopback-test;
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status = "disabled";
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};
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gpio: gpio@18040000 {
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compatible = "qca,ar7240-gpio",
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"qca,ar7100-gpio";
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reg = <0x18040000 0x30>;
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interrupts = <2>;
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ngpios = <18>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pinmux: pinmux@18040028 {
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compatible = "pinctrl-single";
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reg = <0x18040028 0x8>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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jtag_disable_pins: pinmux_jtag_disable_pins {
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pinctrl-single,bits = <0x0 0x1 0x1>;
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};
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switch_led_disable_pins: pinmux_switch_led_disable_pins {
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pinctrl-single,bits = <0x0 0x0 0xf8>;
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};
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clks_disable_pins: pinmux_clks_disable_pins {
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pinctrl-single,bits = <0x0 0x0 0x81f00>;
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};
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};
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pll: pll-controller@18050000 {
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compatible = "qca,ar7240-pll", "syscon";
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reg = <0x18050000 0x3c>;
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clock-names = "ref";
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/* The board must provides the ref clock */
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#clock-cells = <1>;
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clock-output-names = "cpu", "ddr", "ahb";
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};
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wdt: wdt@18060008 {
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compatible = "qca,ar7130-wdt";
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reg = <0x18060008 0x8>;
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interrupts = <4>;
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clocks = <&pll ATH79_CLK_AHB>;
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clock-names = "wdt";
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};
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rst: reset-controller@1806001c {
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compatible = "qca,ar7240-reset",
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"qca,ar7100-reset";
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reg = <0x1806001c 0x4>;
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#reset-cells = <1>;
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};
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pcie: pcie-controller@180c0000 {
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compatible = "qcom,ar7240-pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0x0>;
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reg = <0x180c0000 0x1000>, /* CRP */
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<0x180f0000 0x100>, /* CTRL */
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<0x14000000 0x1000>; /* CFG */
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reg-names = "crp_base", "ctrl_base", "cfg_base";
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ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
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0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 1>;
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interrupt-map = <0 0 0 0 &pcie 0>;
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status = "disabled";
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};
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};
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spi: spi@1f000000 {
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compatible = "qca,ar7240-spi",
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"qca,ar7100-spi";
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reg = <0x1f000000 0x10>;
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clocks = <&pll ATH79_CLK_AHB>;
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clock-names = "ahb";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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&cpuintc {
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qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
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qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
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<&ddr_ctrl 0>, <&ddr_ctrl 1>;
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};
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