9a038e7fd1
Copy config and patches from kernel 5.10 to kernel 5.15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
125 lines
4.1 KiB
Diff
125 lines
4.1 KiB
Diff
From fd0bb28c547f7c8affb1691128cece38f5b626a1 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Thu, 14 Oct 2021 00:39:19 +0200
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Subject: net: dsa: qca8k: move port config to dedicated struct
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Move ports related config to dedicated struct to keep things organized.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 26 +++++++++++++-------------
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drivers/net/dsa/qca8k.h | 10 +++++++---
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2 files changed, 20 insertions(+), 16 deletions(-)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -1019,7 +1019,7 @@ qca8k_parse_port_config(struct qca8k_pri
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delay = 3;
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}
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- priv->rgmii_tx_delay[cpu_port_index] = delay;
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+ priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
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delay = 0;
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@@ -1035,7 +1035,7 @@ qca8k_parse_port_config(struct qca8k_pri
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delay = 3;
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}
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- priv->rgmii_rx_delay[cpu_port_index] = delay;
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+ priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
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/* Skip sgmii parsing for rgmii* mode */
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if (mode == PHY_INTERFACE_MODE_RGMII ||
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@@ -1045,17 +1045,17 @@ qca8k_parse_port_config(struct qca8k_pri
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break;
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if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
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- priv->sgmii_tx_clk_falling_edge = true;
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+ priv->ports_config.sgmii_tx_clk_falling_edge = true;
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if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
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- priv->sgmii_rx_clk_falling_edge = true;
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+ priv->ports_config.sgmii_rx_clk_falling_edge = true;
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if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
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- priv->sgmii_enable_pll = true;
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+ priv->ports_config.sgmii_enable_pll = true;
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if (priv->switch_id == QCA8K_ID_QCA8327) {
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dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
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- priv->sgmii_enable_pll = false;
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+ priv->ports_config.sgmii_enable_pll = false;
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}
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if (priv->switch_revision < 2)
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@@ -1281,15 +1281,15 @@ qca8k_mac_config_setup_internal_delay(st
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* not enabled. With ID or TX/RXID delay is enabled and set
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* to the default and recommended value.
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*/
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- if (priv->rgmii_tx_delay[cpu_port_index]) {
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- delay = priv->rgmii_tx_delay[cpu_port_index];
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+ if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
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+ delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
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val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
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QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
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}
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- if (priv->rgmii_rx_delay[cpu_port_index]) {
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- delay = priv->rgmii_rx_delay[cpu_port_index];
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+ if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
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+ delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
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val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
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QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
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@@ -1397,7 +1397,7 @@ qca8k_phylink_mac_config(struct dsa_swit
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val |= QCA8K_SGMII_EN_SD;
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- if (priv->sgmii_enable_pll)
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+ if (priv->ports_config.sgmii_enable_pll)
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val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
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QCA8K_SGMII_EN_TX;
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@@ -1425,10 +1425,10 @@ qca8k_phylink_mac_config(struct dsa_swit
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val = 0;
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/* SGMII Clock phase configuration */
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- if (priv->sgmii_rx_clk_falling_edge)
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+ if (priv->ports_config.sgmii_rx_clk_falling_edge)
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val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
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- if (priv->sgmii_tx_clk_falling_edge)
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+ if (priv->ports_config.sgmii_tx_clk_falling_edge)
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val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
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if (val)
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -270,15 +270,19 @@ enum {
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QCA8K_CPU_PORT6,
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};
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-struct qca8k_priv {
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- u8 switch_id;
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- u8 switch_revision;
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+struct qca8k_ports_config {
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bool sgmii_rx_clk_falling_edge;
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bool sgmii_tx_clk_falling_edge;
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bool sgmii_enable_pll;
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u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
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u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
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+};
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+
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+struct qca8k_priv {
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+ u8 switch_id;
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+ u8 switch_revision;
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bool legacy_phy_port_mapping;
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+ struct qca8k_ports_config ports_config;
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struct regmap *regmap;
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struct mii_bus *bus;
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struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
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