e4af991220
All patches automatically rebased. Build system: x86_64 Build-tested: bcm2711/RPi4B, mt7622/RT3200 Run-tested: bcm2711/RPi4B, mt7622/RT3200 Signed-off-by: John Audia <therealgraysky@proton.me>
508 lines
22 KiB
Diff
508 lines
22 KiB
Diff
From 90ae68bfc2ffcb54a4ba4f64edbeb84a80cbb57c Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Mon, 22 Nov 2021 16:23:41 +0100
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Subject: net: dsa: qca8k: convert to GENMASK/FIELD_PREP/FIELD_GET
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Convert and try to standardize bit fields using
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GENMASK/FIELD_PREP/FIELD_GET macros. Rework some logic to support the
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standard macro and tidy things up. No functional change intended.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 98 +++++++++++++++----------------
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drivers/net/dsa/qca8k.h | 153 ++++++++++++++++++++++++++----------------------
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2 files changed, 130 insertions(+), 121 deletions(-)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -9,6 +9,7 @@
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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+#include <linux/bitfield.h>
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#include <net/dsa.h>
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#include <linux/of_net.h>
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#include <linux/of_mdio.h>
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@@ -319,18 +320,18 @@ qca8k_fdb_read(struct qca8k_priv *priv,
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}
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/* vid - 83:72 */
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- fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
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+ fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);
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/* aging - 67:64 */
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- fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
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+ fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]);
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/* portmask - 54:48 */
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- fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
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+ fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]);
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/* mac - 47:0 */
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- fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
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- fdb->mac[1] = reg[1] & 0xff;
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- fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
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- fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
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- fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
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- fdb->mac[5] = reg[0] & 0xff;
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+ fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]);
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+ fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]);
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+ fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]);
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+ fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]);
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+ fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]);
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+ fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]);
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return 0;
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}
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@@ -343,18 +344,18 @@ qca8k_fdb_write(struct qca8k_priv *priv,
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int i;
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/* vid - 83:72 */
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- reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
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+ reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);
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/* aging - 67:64 */
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- reg[2] |= aging & QCA8K_ATU_STATUS_M;
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+ reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging);
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/* portmask - 54:48 */
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- reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
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+ reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask);
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/* mac - 47:0 */
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- reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
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- reg[1] |= mac[1];
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- reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
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- reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
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- reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
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- reg[0] |= mac[5];
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+ reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]);
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+ reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]);
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+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]);
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+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]);
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+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]);
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+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
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/* load the array into the ARL table */
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for (i = 0; i < 3; i++)
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@@ -372,7 +373,7 @@ qca8k_fdb_access(struct qca8k_priv *priv
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reg |= cmd;
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if (port >= 0) {
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reg |= QCA8K_ATU_FUNC_PORT_EN;
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- reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
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+ reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port);
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}
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/* Write the function register triggering the table access */
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@@ -454,7 +455,7 @@ qca8k_vlan_access(struct qca8k_priv *pri
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/* Set the command and VLAN index */
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reg = QCA8K_VTU_FUNC1_BUSY;
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reg |= cmd;
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- reg |= vid << QCA8K_VTU_FUNC1_VID_S;
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+ reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid);
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/* Write the function register triggering the table access */
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ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
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@@ -500,13 +501,11 @@ qca8k_vlan_add(struct qca8k_priv *priv,
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if (ret < 0)
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goto out;
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reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
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- reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
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+ reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
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if (untagged)
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- reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<
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- QCA8K_VTU_FUNC0_EG_MODE_S(port);
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+ reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port);
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else
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- reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
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- QCA8K_VTU_FUNC0_EG_MODE_S(port);
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+ reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port);
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ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
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if (ret)
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@@ -534,15 +533,13 @@ qca8k_vlan_del(struct qca8k_priv *priv,
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ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®);
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if (ret < 0)
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goto out;
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- reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
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- reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
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- QCA8K_VTU_FUNC0_EG_MODE_S(port);
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+ reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
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+ reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port);
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/* Check if we're the last member to be removed */
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del = true;
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for (i = 0; i < QCA8K_NUM_PORTS; i++) {
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- mask = QCA8K_VTU_FUNC0_EG_MODE_NOT;
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- mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);
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+ mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
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if ((reg & mask) != mask) {
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del = false;
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@@ -1014,7 +1011,7 @@ qca8k_parse_port_config(struct qca8k_pri
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mode == PHY_INTERFACE_MODE_RGMII_TXID)
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delay = 1;
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- if (delay > QCA8K_MAX_DELAY) {
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+ if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {
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dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
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delay = 3;
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}
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@@ -1030,7 +1027,7 @@ qca8k_parse_port_config(struct qca8k_pri
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mode == PHY_INTERFACE_MODE_RGMII_RXID)
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delay = 2;
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- if (delay > QCA8K_MAX_DELAY) {
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+ if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {
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dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
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delay = 3;
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}
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@@ -1141,8 +1138,8 @@ qca8k_setup(struct dsa_switch *ds)
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/* Enable QCA header mode on all cpu ports */
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if (dsa_is_cpu_port(ds, i)) {
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ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
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- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
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- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
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+ FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
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+ FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
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if (ret) {
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dev_err(priv->dev, "failed enabling QCA header mode");
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return ret;
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@@ -1159,10 +1156,10 @@ qca8k_setup(struct dsa_switch *ds)
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* for igmp, unknown, multicast and broadcast packet
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*/
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ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
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- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
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- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
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- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
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- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
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+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
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+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
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+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
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+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
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if (ret)
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return ret;
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@@ -1180,8 +1177,6 @@ qca8k_setup(struct dsa_switch *ds)
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/* Individual user ports get connected to CPU port only */
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if (dsa_is_user_port(ds, i)) {
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- int shift = 16 * (i % 2);
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-
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER,
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BIT(cpu_port));
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@@ -1198,8 +1193,8 @@ qca8k_setup(struct dsa_switch *ds)
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* default egress vid
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*/
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ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
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- 0xfff << shift,
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- QCA8K_PORT_VID_DEF << shift);
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+ QCA8K_EGREES_VLAN_PORT_MASK(i),
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+ QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));
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if (ret)
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return ret;
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@@ -1246,7 +1241,7 @@ qca8k_setup(struct dsa_switch *ds)
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QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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QCA8K_PORT_HOL_CTRL1_WRED_EN;
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qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
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- QCA8K_PORT_HOL_CTRL1_ING_BUF |
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+ QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
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QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
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QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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QCA8K_PORT_HOL_CTRL1_WRED_EN,
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@@ -1269,8 +1264,8 @@ qca8k_setup(struct dsa_switch *ds)
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mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
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QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
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qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
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- QCA8K_GLOBAL_FC_GOL_XON_THRES_S |
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- QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,
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+ QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
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+ QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
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mask);
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}
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@@ -1935,11 +1930,11 @@ qca8k_port_vlan_filtering(struct dsa_swi
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if (vlan_filtering) {
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
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- QCA8K_PORT_LOOKUP_VLAN_MODE,
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+ QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
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QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
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} else {
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
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- QCA8K_PORT_LOOKUP_VLAN_MODE,
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+ QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
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QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
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}
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@@ -1963,10 +1958,9 @@ qca8k_port_vlan_add(struct dsa_switch *d
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}
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if (pvid) {
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- int shift = 16 * (port % 2);
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-
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ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
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- 0xfff << shift, vlan->vid << shift);
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+ QCA8K_EGREES_VLAN_PORT_MASK(port),
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+ QCA8K_EGREES_VLAN_PORT(port, vlan->vid));
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if (ret)
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return ret;
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@@ -2060,7 +2054,7 @@ static int qca8k_read_switch_id(struct q
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if (ret < 0)
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return -ENODEV;
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- id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);
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+ id = QCA8K_MASK_CTRL_DEVICE_ID(val);
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if (id != data->id) {
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dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id);
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return -ENODEV;
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@@ -2069,7 +2063,7 @@ static int qca8k_read_switch_id(struct q
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priv->switch_id = id;
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/* Save revision to communicate to the internal PHY driver */
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- priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);
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+ priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val);
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return 0;
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}
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -30,9 +30,9 @@
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/* Global control registers */
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#define QCA8K_REG_MASK_CTRL 0x000
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#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
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-#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0)
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+#define QCA8K_MASK_CTRL_REV_ID(x) FIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)
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#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
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-#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
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+#define QCA8K_MASK_CTRL_DEVICE_ID(x) FIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)
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#define QCA8K_REG_PORT0_PAD_CTRL 0x004
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#define QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN BIT(31)
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#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19)
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@@ -41,12 +41,11 @@
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#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
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#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
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#define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22)
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-#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22)
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+#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)
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#define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20)
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-#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20)
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+#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)
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#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
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#define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
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-#define QCA8K_MAX_DELAY 3
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#define QCA8K_PORT_PAD_SGMII_EN BIT(7)
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#define QCA8K_REG_PWS 0x010
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#define QCA8K_PWS_POWER_ON_SEL BIT(31)
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@@ -68,10 +67,12 @@
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#define QCA8K_MDIO_MASTER_READ BIT(27)
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#define QCA8K_MDIO_MASTER_WRITE 0
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#define QCA8K_MDIO_MASTER_SUP_PRE BIT(26)
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-#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21)
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-#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16)
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-#define QCA8K_MDIO_MASTER_DATA(x) (x)
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+#define QCA8K_MDIO_MASTER_PHY_ADDR_MASK GENMASK(25, 21)
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+#define QCA8K_MDIO_MASTER_PHY_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)
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+#define QCA8K_MDIO_MASTER_REG_ADDR_MASK GENMASK(20, 16)
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+#define QCA8K_MDIO_MASTER_REG_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)
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#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
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+#define QCA8K_MDIO_MASTER_DATA(x) FIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)
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#define QCA8K_MDIO_MASTER_MAX_PORTS 5
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#define QCA8K_MDIO_MASTER_MAX_REG 32
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#define QCA8K_GOL_MAC_ADDR0 0x60
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@@ -93,9 +94,7 @@
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#define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
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#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
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#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
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-#define QCA8K_PORT_HDR_CTRL_RX_S 2
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#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
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-#define QCA8K_PORT_HDR_CTRL_TX_S 0
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#define QCA8K_PORT_HDR_CTRL_ALL 2
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#define QCA8K_PORT_HDR_CTRL_MGMT 1
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#define QCA8K_PORT_HDR_CTRL_NONE 0
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@@ -105,10 +104,11 @@
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#define QCA8K_SGMII_EN_TX BIT(3)
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#define QCA8K_SGMII_EN_SD BIT(4)
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#define QCA8K_SGMII_CLK125M_DELAY BIT(7)
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-#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
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-#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
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-#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
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-#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
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+#define QCA8K_SGMII_MODE_CTRL_MASK GENMASK(23, 22)
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+#define QCA8K_SGMII_MODE_CTRL(x) FIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)
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+#define QCA8K_SGMII_MODE_CTRL_BASEX QCA8K_SGMII_MODE_CTRL(0x0)
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+#define QCA8K_SGMII_MODE_CTRL_PHY QCA8K_SGMII_MODE_CTRL(0x1)
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+#define QCA8K_SGMII_MODE_CTRL_MAC QCA8K_SGMII_MODE_CTRL(0x2)
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/* MAC_PWR_SEL registers */
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#define QCA8K_REG_MAC_PWR_SEL 0x0e4
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@@ -121,100 +121,115 @@
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/* ACL registers */
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#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
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-#define QCA8K_PORT_VLAN_CVID(x) (x << 16)
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-#define QCA8K_PORT_VLAN_SVID(x) x
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+#define QCA8K_PORT_VLAN_CVID_MASK GENMASK(27, 16)
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+#define QCA8K_PORT_VLAN_CVID(x) FIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)
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+#define QCA8K_PORT_VLAN_SVID_MASK GENMASK(11, 0)
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+#define QCA8K_PORT_VLAN_SVID(x) FIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)
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#define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
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#define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
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#define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
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/* Lookup registers */
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#define QCA8K_REG_ATU_DATA0 0x600
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-#define QCA8K_ATU_ADDR2_S 24
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-#define QCA8K_ATU_ADDR3_S 16
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-#define QCA8K_ATU_ADDR4_S 8
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+#define QCA8K_ATU_ADDR2_MASK GENMASK(31, 24)
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+#define QCA8K_ATU_ADDR3_MASK GENMASK(23, 16)
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+#define QCA8K_ATU_ADDR4_MASK GENMASK(15, 8)
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+#define QCA8K_ATU_ADDR5_MASK GENMASK(7, 0)
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#define QCA8K_REG_ATU_DATA1 0x604
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-#define QCA8K_ATU_PORT_M 0x7f
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-#define QCA8K_ATU_PORT_S 16
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-#define QCA8K_ATU_ADDR0_S 8
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+#define QCA8K_ATU_PORT_MASK GENMASK(22, 16)
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+#define QCA8K_ATU_ADDR0_MASK GENMASK(15, 8)
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+#define QCA8K_ATU_ADDR1_MASK GENMASK(7, 0)
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#define QCA8K_REG_ATU_DATA2 0x608
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-#define QCA8K_ATU_VID_M 0xfff
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-#define QCA8K_ATU_VID_S 8
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-#define QCA8K_ATU_STATUS_M 0xf
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+#define QCA8K_ATU_VID_MASK GENMASK(19, 8)
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+#define QCA8K_ATU_STATUS_MASK GENMASK(3, 0)
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#define QCA8K_ATU_STATUS_STATIC 0xf
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#define QCA8K_REG_ATU_FUNC 0x60c
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#define QCA8K_ATU_FUNC_BUSY BIT(31)
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#define QCA8K_ATU_FUNC_PORT_EN BIT(14)
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#define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
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#define QCA8K_ATU_FUNC_FULL BIT(12)
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-#define QCA8K_ATU_FUNC_PORT_M 0xf
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-#define QCA8K_ATU_FUNC_PORT_S 8
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+#define QCA8K_ATU_FUNC_PORT_MASK GENMASK(11, 8)
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#define QCA8K_REG_VTU_FUNC0 0x610
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#define QCA8K_VTU_FUNC0_VALID BIT(20)
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#define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
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-#define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
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-#define QCA8K_VTU_FUNC0_EG_MODE_MASK 3
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-#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
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-#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1
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-#define QCA8K_VTU_FUNC0_EG_MODE_TAG 2
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-#define QCA8K_VTU_FUNC0_EG_MODE_NOT 3
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+/* QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(17, 4)
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+ * It does contain VLAN_MODE for each port [5:4] for port0,
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+ * [7:6] for port1 ... [17:16] for port6. Use virtual port
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+ * define to handle this.
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+ */
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+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i) (4 + (_i) * 2)
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+#define QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(1, 0)
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+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i) (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
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+#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)
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+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
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+#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)
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+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
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+#define QCA8K_VTU_FUNC0_EG_MODE_TAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)
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+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
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+#define QCA8K_VTU_FUNC0_EG_MODE_NOT FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)
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+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i) (QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
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#define QCA8K_REG_VTU_FUNC1 0x614
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#define QCA8K_VTU_FUNC1_BUSY BIT(31)
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-#define QCA8K_VTU_FUNC1_VID_S 16
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+#define QCA8K_VTU_FUNC1_VID_MASK GENMASK(27, 16)
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#define QCA8K_VTU_FUNC1_FULL BIT(4)
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#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
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#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
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#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
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-#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
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-#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
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-#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
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-#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
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+#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)
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+#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)
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+#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK GENMASK(14, 8)
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+#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK GENMASK(6, 0)
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#define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
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#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
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-#define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8)
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-#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
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-#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8)
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-#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8)
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-#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8)
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+#define QCA8K_PORT_LOOKUP_VLAN_MODE_MASK GENMASK(9, 8)
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+#define QCA8K_PORT_LOOKUP_VLAN_MODE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)
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+#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE QCA8K_PORT_LOOKUP_VLAN_MODE(0x0)
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+#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK QCA8K_PORT_LOOKUP_VLAN_MODE(0x1)
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+#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK QCA8K_PORT_LOOKUP_VLAN_MODE(0x2)
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+#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE QCA8K_PORT_LOOKUP_VLAN_MODE(0x3)
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#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
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-#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
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-#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
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-#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
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-#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
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-#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
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-#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
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+#define QCA8K_PORT_LOOKUP_STATE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)
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+#define QCA8K_PORT_LOOKUP_STATE_DISABLED QCA8K_PORT_LOOKUP_STATE(0x0)
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+#define QCA8K_PORT_LOOKUP_STATE_BLOCKING QCA8K_PORT_LOOKUP_STATE(0x1)
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+#define QCA8K_PORT_LOOKUP_STATE_LISTENING QCA8K_PORT_LOOKUP_STATE(0x2)
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+#define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
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+#define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
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#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
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#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
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-#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16)
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-#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16)
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-#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0)
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-#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0)
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+#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16)
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+#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)
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+#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK GENMASK(8, 0)
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+#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)
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#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24)
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-#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK GENMASK(3, 0)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK GENMASK(7, 4)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK GENMASK(11, 8)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK GENMASK(15, 12)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK GENMASK(19, 16)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK GENMASK(23, 20)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK GENMASK(29, 24)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)
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#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
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-#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0)
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-#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0)
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+#define QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK GENMASK(3, 0)
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+#define QCA8K_PORT_HOL_CTRL1_ING(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)
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#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
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#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
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#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
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#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
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/* Pkt edit registers */
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+#define QCA8K_EGREES_VLAN_PORT_SHIFT(_i) (16 * ((_i) % 2))
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+#define QCA8K_EGREES_VLAN_PORT_MASK(_i) (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
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+#define QCA8K_EGREES_VLAN_PORT(_i, x) ((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
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#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
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/* L3 registers */
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