3a4b751110
The uart node is enabled on all devices except one (GL-USB150 *). Thus, let's not have a few hundred nodes to enable it, but do not disable it in the first place. Where the majority of devices is using it, also move the serial0 alias to the DTSI. *) Since GL-USB150 even defines serial0 alias, the missing uart is probably just a mistake. Anyway, disable it for now so this patch stays cosmetic. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
212 lines
3.4 KiB
Plaintext
212 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "ar9344.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "PowerCloud Systems CR5000";
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compatible = "pcs,cr5000", "qca,ar9344";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&jtag_disable_pins>;
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reset {
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label = "Reset button";
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linux,code = <KEY_RESTART>;
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gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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wps {
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label = "WPS button";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_power: power {
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label = "amber:power";
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>,
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<&gpio 4 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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wlan2g {
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label = "blue:wlan";
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gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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wps_white {
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label = "white:wps";
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gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&ref {
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clock-frequency = <25000000>;
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};
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&spi {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <25000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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uboot: partition@0 {
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label = "u-boot";
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reg = <0x000000 0x040000>;
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read-only;
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};
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partition@40000 {
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label = "u-boot-env";
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reg = <0x040000 0x010000>;
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read-only;
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};
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partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x050000 0x07a0000>;
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};
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art: partition@7f0000 {
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label = "art";
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reg = <0x7f0000 0x010000>;
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read-only;
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};
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};
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};
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};
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&usb {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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hub_port1: port@1 {
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reg = <1>;
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#trigger-source-cells = <0>;
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};
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};
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&usb_phy {
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status = "okay";
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};
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&pcie {
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status = "okay";
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ath9k: wifi@0,0 {
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compatible = "pci168c,0030";
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reg = <0x0000 0 0 0 0>;
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mtd-mac-address = <&art 0x5002>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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&mdio0 {
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status = "okay";
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phy-mask = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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phy-mode = "rgmii";
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qca,ar8327-initvals = <
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0x04 0x07600000 /* PORT0 PAD MODE CTRL */
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0x10 0x81000080 /* POWER_ON_STRAP */
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0x50 0xcc35cc35 /* LED_CTRL0 */
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0x54 0xca35ca35 /* LED_CTRL1 */
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0x58 0xc935c935 /* LED_CTRL2 */
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0x5c 0x03ffff00 /* LED_CTRL3 */
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0x7c 0x0000007e /* PORT0_STATUS */
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>;
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};
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};
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ð0 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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/* default for ar934x, except for 1000M */
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pll-data = <0x06000000 0x00000101 0x00001616>;
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mtd-mac-address = <&art 0x0>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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aliases {
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ag0 = ð1;
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};
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port@0 {
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compatible = "swconfig,port";
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reg = <0>;
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swconfig,segment = "lan";
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swconfig,portmap = <1 1>;
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};
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port@1 {
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compatible = "swconfig,port";
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reg = <1>;
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swconfig,segment = "lan";
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swconfig,portmap = <2 2>;
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};
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port@2 {
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compatible = "swconfig,port";
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reg = <2>;
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swconfig,segment = "lan";
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swconfig,portmap = <3 3>;
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};
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port@3 {
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compatible = "swconfig,port";
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reg = <3>;
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swconfig,segment = "lan";
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swconfig,portmap = <4 4>;
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};
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port@4 {
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compatible = "swconfig,port";
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reg = <4>;
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swconfig,segment = "wan";
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swconfig,portmap = <5 5>;
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};
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};
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&wmac {
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status = "okay";
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mtd-cal-data = <&art 0x1000>;
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};
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