02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
254 lines
5.9 KiB
Diff
254 lines
5.9 KiB
Diff
From 1c6e51ffb10f5bf93a3018c7c1e04d7ed93f944e Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Fri, 7 Mar 2014 10:56:59 -0600
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Subject: [PATCH 130/182] ARM: qcom: Add initial IPQ8064 SoC and AP148 device
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trees
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Add basic IPQ8064 SoC include device tree and support for basic booting on
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the AP148 Reference board.
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/boot/dts/Makefile | 1 +
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 25 +++++
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arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 1 +
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 176 ++++++++++++++++++++++++++++++
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arch/arm/mach-qcom/board.c | 2 +
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5 files changed, 205 insertions(+)
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create mode 100644 arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
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create mode 100644 arch/arm/boot/dts/qcom-ipq8064.dtsi
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -235,6 +235,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-apq8064-ifc6410.dtb \
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qcom-apq8074-dragonboard.dtb \
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qcom-apq8084-mtp.dtb \
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+ qcom-ipq8064-ap148.dtb \
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qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb
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dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -0,0 +1,25 @@
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+#include "qcom-ipq8064-v1.0.dtsi"
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+
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+/ {
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+ model = "Qualcomm IPQ8064/AP148";
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+ compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
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+
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+ reserved-memory {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ rsvd@41200000 {
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+ reg = <0x41200000 0x300000>;
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+ no-map;
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+ };
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+ };
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+
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+ soc {
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+ gsbi@16300000 {
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+ qcom,mode = <GSBI_PROT_I2C_UART>;
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+ status = "ok";
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+ serial@16340000 {
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+ status = "ok";
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+ };
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
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@@ -0,0 +1 @@
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+#include "qcom-ipq8064.dtsi"
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -0,0 +1,176 @@
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+/dts-v1/;
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+
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+#include "skeleton.dtsi"
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+#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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+#include <dt-bindings/soc/qcom,gsbi.h>
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+
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+/ {
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+ model = "Qualcomm IPQ8064";
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+ compatible = "qcom,ipq8064";
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+ interrupt-parent = <&intc>;
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu@0 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v1";
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+ device_type = "cpu";
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+ reg = <0>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc0>;
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+ qcom,saw = <&saw0>;
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+ };
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+
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+ cpu@1 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v1";
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+ device_type = "cpu";
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+ reg = <1>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc1>;
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+ qcom,saw = <&saw1>;
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+ };
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+
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+ L2: l2-cache {
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+ compatible = "cache";
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+ cache-level = <2>;
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+ };
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+ };
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+
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+ cpu-pmu {
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+ compatible = "qcom,krait-pmu";
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+ interrupts = <1 10 0x304>;
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+ };
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+
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+ reserved-memory {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ nss@40000000 {
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+ reg = <0x40000000 0x1000000>;
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+ no-map;
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+ };
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+
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+ smem@41000000 {
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+ reg = <0x41000000 0x200000>;
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+ no-map;
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+ };
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+ };
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+
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+ soc: soc {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ compatible = "simple-bus";
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+
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+ qcom_pinmux: pinmux@800000 {
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+ compatible = "qcom,ipq8064-pinctrl";
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+ reg = <0x800000 0x4000>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ interrupts = <0 32 0x4>;
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+ };
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+
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+ intc: interrupt-controller@2000000 {
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+ compatible = "qcom,msm-qgic2";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ reg = <0x02000000 0x1000>,
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+ <0x02002000 0x1000>;
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+ };
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+
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+ timer@200a000 {
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+ compatible = "qcom,kpss-timer", "qcom,msm-timer";
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+ interrupts = <1 1 0x301>,
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+ <1 2 0x301>,
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+ <1 3 0x301>;
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+ reg = <0x0200a000 0x100>;
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+ clock-frequency = <25000000>,
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+ <32768>;
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+ cpu-offset = <0x80000>;
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+ };
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+
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+ acc0: clock-controller@2088000 {
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+ compatible = "qcom,kpss-acc-v1";
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+ reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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+ };
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+
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+ acc1: clock-controller@2098000 {
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+ compatible = "qcom,kpss-acc-v1";
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+ reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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+ };
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+
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+ saw0: regulator@2089000 {
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+ compatible = "qcom,saw2";
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+ reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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+ regulator;
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+ };
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+
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+ saw1: regulator@2099000 {
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+ compatible = "qcom,saw2";
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+ reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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+ regulator;
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+ };
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+
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+ gsbi2: gsbi@12480000 {
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+ compatible = "qcom,gsbi-v1.0.0";
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+ reg = <0x12480000 0x100>;
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+ clocks = <&gcc GSBI2_H_CLK>;
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+ clock-names = "iface";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ status = "disabled";
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+
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+ serial@12490000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x12490000 0x1000>,
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+ <0x12480000 0x1000>;
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+ interrupts = <0 195 0x0>;
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+ clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+ };
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+
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+ gsbi4: gsbi@16300000 {
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+ compatible = "qcom,gsbi-v1.0.0";
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+ reg = <0x16300000 0x100>;
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+ clocks = <&gcc GSBI4_H_CLK>;
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+ clock-names = "iface";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ status = "disabled";
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+
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+ serial@16340000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x16340000 0x1000>,
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+ <0x16300000 0x1000>;
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+ interrupts = <0 152 0x0>;
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+ clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+ };
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+
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+ qcom,ssbi@500000 {
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+ compatible = "qcom,ssbi";
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+ reg = <0x00500000 0x1000>;
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+ qcom,controller-type = "pmic-arbiter";
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+ };
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+
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+ gcc: clock-controller@900000 {
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+ compatible = "qcom,gcc-ipq8064";
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+ reg = <0x00900000 0x4000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+ };
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+};
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--- a/arch/arm/mach-qcom/board.c
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+++ b/arch/arm/mach-qcom/board.c
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@@ -18,6 +18,8 @@ static const char * const qcom_dt_match[
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"qcom,apq8064",
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"qcom,apq8074-dragonboard",
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"qcom,apq8084",
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+ "qcom,ipq8062",
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+ "qcom,ipq8064",
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"qcom,msm8660-surf",
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"qcom,msm8960-cdp",
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NULL
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