02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
109 lines
2.3 KiB
Diff
109 lines
2.3 KiB
Diff
From 4490cfa66379909cdddc3518c8e75b7cd26d8f69 Mon Sep 17 00:00:00 2001
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From: Andy Gross <agross@codeaurora.org>
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Date: Mon, 16 Jun 2014 16:53:49 -0500
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Subject: [PATCH 151/182] ARM: ipq8064: Add nand device info
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 34 ++++++++++++++++++++++++++++++
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 33 +++++++++++++++++++++++++++++
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2 files changed, 67 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -45,6 +45,29 @@
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bias-none;
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};
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};
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+ nand_pins: nand_pins {
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+ mux {
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+ pins = "gpio34", "gpio35", "gpio36",
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+ "gpio37", "gpio38", "gpio39",
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+ "gpio40", "gpio41", "gpio42",
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+ "gpio43", "gpio44", "gpio45",
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+ "gpio46", "gpio47";
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+ function = "nand";
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+ drive-strength = <10>;
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+ bias-disable;
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+ };
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+ pullups {
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+ pins = "gpio39";
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+ bias-pull-up;
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+ };
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+ hold {
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+ pins = "gpio40", "gpio41", "gpio42",
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+ "gpio43", "gpio44", "gpio45",
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+ "gpio46", "gpio47";
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+ bias-bus-hold;
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+ };
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+ };
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+
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};
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gsbi@16300000 {
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@@ -126,5 +149,16 @@
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sata@29000000 {
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status = "ok";
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};
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+
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+ dma@18300000 {
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+ status = "ok";
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+ };
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+
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+ nand@0x1ac00000 {
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+ status = "ok";
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+
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+ pinctrl-0 = <&nand_pins>;
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+ pinctrl-names = "default";
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -76,6 +76,7 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 32 0x4>;
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+
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};
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intc: interrupt-controller@2000000 {
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@@ -369,5 +370,37 @@
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phy-names = "sata-phy";
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status = "disabled";
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};
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+
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+ adm_dma: dma@18300000 {
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+ compatible = "qcom,adm";
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+ reg = <0x18300000 0x100000>;
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+ interrupts = <0 170 0>;
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+
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+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
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+ clock-names = "core_clk", "iface_clk";
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+
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+ resets = <&gcc ADM0_RESET>,
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+ <&gcc ADM0_PBUS_RESET>,
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+ <&gcc ADM0_C0_RESET>,
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+ <&gcc ADM0_C1_RESET>,
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+ <&gcc ADM0_C2_RESET>;
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+
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+ reset-names = "adm", "pbus", "c0", "c1", "c2";
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+
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+ status = "disabled";
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+ };
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+
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+ nand@0x1ac00000 {
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+ compatible = "qcom,qcom_nand";
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+ reg = <0x1ac00000 0x800>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ clocks = <&gcc EBI2_CLK>;
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+ clock-names = "core_clk";
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+
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+
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+ status = "disabled";
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+ };
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};
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};
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