02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
84 lines
2.1 KiB
Diff
84 lines
2.1 KiB
Diff
From c78ae23b6c174c9f2e0973a247942b6b4adb7e82 Mon Sep 17 00:00:00 2001
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From: Andy Gross <agross@codeaurora.org>
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Date: Thu, 26 Jun 2014 13:02:59 -0500
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Subject: [PATCH 180/182] ARM: dts: Add ADM DMA nodes and SPI linkage
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This patch adds the ADM DMA controller DT nodes and also enables the use of dma
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in SPI.
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 11 +++++++++++
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++---
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2 files changed, 16 insertions(+), 3 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -44,6 +44,10 @@
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drive-strength = <10>;
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bias-none;
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};
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+ cs {
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+ pins = "gpio20";
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+ drive-strength = <12>;
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+ };
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};
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nand_pins: nand_pins {
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mux {
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@@ -100,12 +104,17 @@
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cs-gpios = <&qcom_pinmux 20 0>;
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+ dmas = <&adm_dma 6 9>,
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+ <&adm_dma 5 10>;
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+ dma-names = "rx", "tx";
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+
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flash: m25p80@0 {
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compatible = "s25fl256s1";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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+ m25p,fast-read;
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partition@0 {
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label = "rootfs";
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@@ -140,8 +149,10 @@
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ranges = <0x00000000 0 0x00000000 0x31f00000 0 0x00100000 /* configuration space */
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0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */
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0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
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+
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};
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+
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sata-phy@1b400000 {
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status = "ok";
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -421,19 +421,21 @@
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compatible = "qcom,adm";
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reg = <0x18300000 0x100000>;
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interrupts = <0 170 0>;
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+ #dma-cells = <2>;
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clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
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- clock-names = "core_clk", "iface_clk";
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+ clock-names = "core", "iface";
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resets = <&gcc ADM0_RESET>,
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<&gcc ADM0_PBUS_RESET>,
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<&gcc ADM0_C0_RESET>,
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<&gcc ADM0_C1_RESET>,
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<&gcc ADM0_C2_RESET>;
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-
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- reset-names = "adm", "pbus", "c0", "c1", "c2";
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+ reset-names = "clk", "pbus", "c0", "c1", "c2";
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+ qcom,ee = <0>;
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status = "disabled";
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+
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};
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nand@0x1ac00000 {
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