8d4c22a956
For all SoC in the ath79 target, the PLL controller provides 3 main clocks "cpu", "ddr" and "ahb" through the input clock "ref". Signed-off-by: Shiji Yang <yangshiji66@qq.com>
8 lines
112 B
Plaintext
8 lines
112 B
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "ar9330.dtsi"
|
|
|
|
/ {
|
|
compatible = "qca,ar9331";
|
|
};
|