ba6096d04b
OpenWRT's developer guide prefers having actual patches so they an be sent upstream more easily. However, in this case, Adding proper fields also allows for `git am` to properly function. Some of these patches are quite old, and lack much traceable history. This commit tries to rectify that, by digging in the history to find where and how it was first added. It is by no means perfect and also shows some patches that should have been long gone. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
150 lines
4.1 KiB
Diff
150 lines
4.1 KiB
Diff
From: John Crispin <john@phrozen.org>
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Subject: ath79: fix remove irq code from pci driver patch
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This patch got mangled in the void while rebasing it.
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Submitted-by: John Crispin <john@phrozen.org>
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---
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arch/mips/pci/pci-ar71xx.c | 107 ------------------
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1 file changed, 141 deletions(-)
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--- a/arch/mips/pci/pci-ar71xx.c
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+++ b/arch/mips/pci/pci-ar71xx.c
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@@ -51,11 +51,9 @@
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struct ar71xx_pci_controller {
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struct device_node *np;
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void __iomem *cfg_base;
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- int irq;
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struct pci_controller pci_ctrl;
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struct resource io_res;
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struct resource mem_res;
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- struct irq_domain *domain;
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};
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/* Byte lane enable bits */
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@@ -227,104 +225,6 @@ static struct pci_ops ar71xx_pci_ops = {
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.write = ar71xx_pci_write_config,
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};
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-static void ar71xx_pci_irq_handler(struct irq_desc *desc)
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-{
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- void __iomem *base = ath79_reset_base;
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- struct irq_chip *chip = irq_desc_get_chip(desc);
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- struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
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- u32 pending;
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-
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- chained_irq_enter(chip, desc);
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- pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
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- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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-
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- if (pending & AR71XX_PCI_INT_DEV0)
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- generic_handle_irq(irq_linear_revmap(apc->domain, 1));
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-
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- else if (pending & AR71XX_PCI_INT_DEV1)
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- generic_handle_irq(irq_linear_revmap(apc->domain, 2));
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-
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- else if (pending & AR71XX_PCI_INT_DEV2)
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- generic_handle_irq(irq_linear_revmap(apc->domain, 3));
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-
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- else if (pending & AR71XX_PCI_INT_CORE)
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- generic_handle_irq(irq_linear_revmap(apc->domain, 4));
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-
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- else
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- spurious_interrupt();
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- chained_irq_exit(chip, desc);
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-}
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-
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-static void ar71xx_pci_irq_unmask(struct irq_data *d)
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-{
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- struct ar71xx_pci_controller *apc;
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- unsigned int irq;
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- void __iomem *base = ath79_reset_base;
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- u32 t;
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-
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- apc = irq_data_get_irq_chip_data(d);
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- irq = irq_linear_revmap(apc->domain, d->irq);
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-
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- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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- __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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-
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- /* flush write */
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- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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-}
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-
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-static void ar71xx_pci_irq_mask(struct irq_data *d)
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-{
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- struct ar71xx_pci_controller *apc;
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- unsigned int irq;
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- void __iomem *base = ath79_reset_base;
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- u32 t;
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-
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- apc = irq_data_get_irq_chip_data(d);
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- irq = irq_linear_revmap(apc->domain, d->irq);
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-
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- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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- __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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-
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- /* flush write */
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- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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-}
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-
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-static struct irq_chip ar71xx_pci_irq_chip = {
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- .name = "AR71XX PCI",
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- .irq_mask = ar71xx_pci_irq_mask,
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- .irq_unmask = ar71xx_pci_irq_unmask,
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- .irq_mask_ack = ar71xx_pci_irq_mask,
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-};
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-
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-static int ar71xx_pci_irq_map(struct irq_domain *d,
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- unsigned int irq, irq_hw_number_t hw)
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-{
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- struct ar71xx_pci_controller *apc = d->host_data;
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-
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- irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
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- irq_set_chip_data(irq, apc);
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-
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- return 0;
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-}
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-
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-static const struct irq_domain_ops ar71xx_pci_domain_ops = {
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- .xlate = irq_domain_xlate_onecell,
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- .map = ar71xx_pci_irq_map,
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-};
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-
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-static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
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-{
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- void __iomem *base = ath79_reset_base;
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-
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- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
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-
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- apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
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- &ar71xx_pci_domain_ops, apc);
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- irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
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- apc);
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-}
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-
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static void ar71xx_pci_reset(void)
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{
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ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
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@@ -358,10 +258,6 @@ static int ar71xx_pci_probe(struct platf
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if (IS_ERR(apc->cfg_base))
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return PTR_ERR(apc->cfg_base);
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- apc->irq = platform_get_irq(pdev, 0);
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- if (apc->irq < 0)
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- return -EINVAL;
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-
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ar71xx_pci_reset();
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/* setup COMMAND register */
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@@ -372,8 +268,6 @@ static int ar71xx_pci_probe(struct platf
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/* clear bus errors */
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ar71xx_pci_check_error(apc, 1);
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- ar71xx_pci_irq_init(apc);
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-
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apc->np = pdev->dev.of_node;
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apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
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apc->pci_ctrl.mem_resource = &apc->mem_res;
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