ba6096d04b
OpenWRT's developer guide prefers having actual patches so they an be sent upstream more easily. However, in this case, Adding proper fields also allows for `git am` to properly function. Some of these patches are quite old, and lack much traceable history. This commit tries to rectify that, by digging in the history to find where and how it was first added. It is by no means perfect and also shows some patches that should have been long gone. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
68 lines
2.3 KiB
Diff
68 lines
2.3 KiB
Diff
From: Daniel Golle <daniel@makrotopia.org>
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Subject: [PATCH] ath79: add support for Atheros AR934x HS UART
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AR934x chips also got the 'old' qca,ar9330-uart in addition to the
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'new' ns16550a compatible one. Add support for UART1 clock selector as
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well as device-tree bindings in ar934x.dtsi to make use of that uart.
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Reported-by: Piotr Dymacz <pepe2k@gmail.com>
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Submitted-by: Daniel Golle <daniel@makrotopia.org>
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---
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arch/mips/ath79/clock.c | 7 +++++++
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.../mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
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include/dt-bindings/clock/ath79-clk.h | 3 ++-
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3 files changed, 10 insertions(+), 1 deletion(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -40,6 +40,7 @@ static const char * const clk_names[ATH7
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[ATH79_CLK_AHB] = "ahb",
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[ATH79_CLK_REF] = "ref",
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[ATH79_CLK_MDIO] = "mdio",
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+ [ATH79_CLK_UART1] = "uart1",
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};
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static const char * __init ath79_clk_name(int type)
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@@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo
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if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
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ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
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+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)
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+ ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);
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+
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iounmap(dpll_base);
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}
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@@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt(
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if (!clks[ATH79_CLK_MDIO])
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clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
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+ if (!clks[ATH79_CLK_UART1])
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+ clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];
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+
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if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
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pr_err("%pOF: could not register clk provider\n", np);
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goto err_iounmap;
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -348,6 +348,7 @@
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
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+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL BIT(7)
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#define QCA953X_PLL_CPU_CONFIG_REG 0x00
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#define QCA953X_PLL_DDR_CONFIG_REG 0x04
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--- a/include/dt-bindings/clock/ath79-clk.h
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+++ b/include/dt-bindings/clock/ath79-clk.h
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@@ -11,7 +11,8 @@
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#define ATH79_CLK_AHB 2
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#define ATH79_CLK_REF 3
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#define ATH79_CLK_MDIO 4
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+#define ATH79_CLK_UART1 5
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-#define ATH79_CLK_END 5
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+#define ATH79_CLK_END 6
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#endif /* __DT_BINDINGS_ATH79_CLK_H */
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