b1f21329d4
Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in. It shares most of the stuff with its external counterpart, however it is modified for the SoC. Namely, it doesn't have second CPU port (Port 6), so it has 6 ports instead of 7. It also has no built-in PHY-s but rather requires external PSGMII based companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry out calibration before using them. PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which unfortunately requires some magic values as the datasheet doesnt document the bits that are being set or the register at all. Since its built-in it is MMIO like other peripherals and doesn't have its own MDIO bus but depends on the SoC provided one. CPU connection is at Port 0 and it uses some kind of a internal connection and no traditional RGMII/SGMII. It also doesn't use in-band tagging like other qca8k switches so a shinfo based tagger is used. This is based on the current OpenWrt qca8k version that has been imported from generic target. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
62 lines
1.5 KiB
Diff
62 lines
1.5 KiB
Diff
From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Fri, 2 Oct 2020 10:43:26 +0200
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Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
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This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++
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1 file changed, 18 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -8,6 +8,7 @@
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#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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+#include <dt-bindings/net/qcom-qca807x.h>
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/ {
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#address-cells = <1>;
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@@ -726,22 +727,38 @@
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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+
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+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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+
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+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
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};
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ethphy2: ethernet-phy@2 {
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reg = <2>;
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+
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+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
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};
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ethphy3: ethernet-phy@3 {
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reg = <3>;
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+
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+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
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};
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ethphy4: ethernet-phy@4 {
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reg = <4>;
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+
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+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
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+ };
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+
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+ psgmiiphy: psgmii-phy@5 {
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+ reg = <5>;
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+
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+ qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;
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};
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};
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