![Christian Marangi](/assets/img/avatar_default.png)
Replace nandc fix patch with upstream version. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
269 lines
8.1 KiB
Diff
269 lines
8.1 KiB
Diff
From b360514edb4743cbf86fc377699c75e98b1264c7 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 16 Jun 2022 02:18:33 +0200
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Subject: [PATCH 1/2] mtd: nand: raw: qcom_nandc: reorder qcom_nand_host struct
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Reorder structs in nandc driver to save holes.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Link: https://lore.kernel.org/linux-mtd/20220616001835.24393-2-ansuelsmth@gmail.com
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---
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drivers/mtd/nand/raw/qcom_nandc.c | 107 +++++++++++++++++-------------
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1 file changed, 62 insertions(+), 45 deletions(-)
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--- a/drivers/mtd/nand/raw/qcom_nandc.c
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+++ b/drivers/mtd/nand/raw/qcom_nandc.c
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@@ -237,6 +237,9 @@ nandc_set_reg(chip, reg, \
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* @bam_ce - the array of BAM command elements
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* @cmd_sgl - sgl for NAND BAM command pipe
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* @data_sgl - sgl for NAND BAM consumer/producer pipe
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+ * @last_data_desc - last DMA desc in data channel (tx/rx).
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+ * @last_cmd_desc - last DMA desc in command channel.
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+ * @txn_done - completion for NAND transfer.
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* @bam_ce_pos - the index in bam_ce which is available for next sgl
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* @bam_ce_start - the index in bam_ce which marks the start position ce
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* for current sgl. It will be used for size calculation
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@@ -249,14 +252,14 @@ nandc_set_reg(chip, reg, \
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* @rx_sgl_start - start index in data sgl for rx.
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* @wait_second_completion - wait for second DMA desc completion before making
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* the NAND transfer completion.
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- * @txn_done - completion for NAND transfer.
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- * @last_data_desc - last DMA desc in data channel (tx/rx).
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- * @last_cmd_desc - last DMA desc in command channel.
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*/
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struct bam_transaction {
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struct bam_cmd_element *bam_ce;
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struct scatterlist *cmd_sgl;
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struct scatterlist *data_sgl;
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+ struct dma_async_tx_descriptor *last_data_desc;
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+ struct dma_async_tx_descriptor *last_cmd_desc;
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+ struct completion txn_done;
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u32 bam_ce_pos;
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u32 bam_ce_start;
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u32 cmd_sgl_pos;
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@@ -266,25 +269,23 @@ struct bam_transaction {
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u32 rx_sgl_pos;
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u32 rx_sgl_start;
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bool wait_second_completion;
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- struct completion txn_done;
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- struct dma_async_tx_descriptor *last_data_desc;
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- struct dma_async_tx_descriptor *last_cmd_desc;
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};
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/*
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* This data type corresponds to the nand dma descriptor
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+ * @dma_desc - low level DMA engine descriptor
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* @list - list for desc_info
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- * @dir - DMA transfer direction
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+ *
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* @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
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* ADM
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* @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
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* @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
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- * @dma_desc - low level DMA engine descriptor
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+ * @dir - DMA transfer direction
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*/
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struct desc_info {
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+ struct dma_async_tx_descriptor *dma_desc;
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struct list_head node;
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- enum dma_data_direction dir;
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union {
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struct scatterlist adm_sgl;
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struct {
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@@ -292,7 +293,7 @@ struct desc_info {
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int sgl_cnt;
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};
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};
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- struct dma_async_tx_descriptor *dma_desc;
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+ enum dma_data_direction dir;
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};
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/*
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@@ -336,52 +337,64 @@ struct nandc_regs {
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/*
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* NAND controller data struct
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*
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- * @controller: base controller structure
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- * @host_list: list containing all the chips attached to the
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- * controller
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* @dev: parent device
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+ *
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* @base: MMIO base
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- * @base_phys: physical base address of controller registers
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- * @base_dma: dma base address of controller registers
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+ *
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* @core_clk: controller clock
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* @aon_clk: another controller clock
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*
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+ * @regs: a contiguous chunk of memory for DMA register
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+ * writes. contains the register values to be
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+ * written to controller
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+ *
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+ * @props: properties of current NAND controller,
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+ * initialized via DT match data
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+ *
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+ * @controller: base controller structure
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+ * @host_list: list containing all the chips attached to the
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+ * controller
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+ *
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* @chan: dma channel
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* @cmd_crci: ADM DMA CRCI for command flow control
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* @data_crci: ADM DMA CRCI for data flow control
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+ *
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* @desc_list: DMA descriptor list (list of desc_infos)
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*
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* @data_buffer: our local DMA buffer for page read/writes,
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* used when we can't use the buffer provided
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* by upper layers directly
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- * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
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- * functions
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* @reg_read_buf: local buffer for reading back registers via DMA
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+ *
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+ * @base_phys: physical base address of controller registers
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+ * @base_dma: dma base address of controller registers
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* @reg_read_dma: contains dma address for register read buffer
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- * @reg_read_pos: marker for data read in reg_read_buf
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*
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- * @regs: a contiguous chunk of memory for DMA register
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- * writes. contains the register values to be
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- * written to controller
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- * @cmd1/vld: some fixed controller register values
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- * @props: properties of current NAND controller,
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- * initialized via DT match data
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+ * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
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+ * functions
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* @max_cwperpage: maximum QPIC codewords required. calculated
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* from all connected NAND devices pagesize
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+ *
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+ * @reg_read_pos: marker for data read in reg_read_buf
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+ *
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+ * @cmd1/vld: some fixed controller register values
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*/
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struct qcom_nand_controller {
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- struct nand_controller controller;
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- struct list_head host_list;
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-
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struct device *dev;
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void __iomem *base;
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- phys_addr_t base_phys;
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- dma_addr_t base_dma;
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struct clk *core_clk;
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struct clk *aon_clk;
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+ struct nandc_regs *regs;
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+ struct bam_transaction *bam_txn;
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+
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+ const struct qcom_nandc_props *props;
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+
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+ struct nand_controller controller;
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+ struct list_head host_list;
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+
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union {
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/* will be used only by QPIC for BAM DMA */
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struct {
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@@ -399,22 +412,22 @@ struct qcom_nand_controller {
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};
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struct list_head desc_list;
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- struct bam_transaction *bam_txn;
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u8 *data_buffer;
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+ __le32 *reg_read_buf;
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+
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+ phys_addr_t base_phys;
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+ dma_addr_t base_dma;
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+ dma_addr_t reg_read_dma;
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+
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int buf_size;
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int buf_count;
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int buf_start;
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unsigned int max_cwperpage;
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- __le32 *reg_read_buf;
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- dma_addr_t reg_read_dma;
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int reg_read_pos;
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- struct nandc_regs *regs;
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-
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u32 cmd1, vld;
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- const struct qcom_nandc_props *props;
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};
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/*
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@@ -430,19 +443,21 @@ struct qcom_nand_controller {
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* and reserved bytes
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* @cw_data: the number of bytes within a codeword protected
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* by ECC
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- * @use_ecc: request the controller to use ECC for the
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- * upcoming read/write
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- * @bch_enabled: flag to tell whether BCH ECC mode is used
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* @ecc_bytes_hw: ECC bytes used by controller hardware for this
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* chip
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- * @status: value to be returned if NAND_CMD_STATUS command
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- * is executed
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+ *
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* @last_command: keeps track of last command on this chip. used
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* for reading correct status
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*
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* @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
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* ecc/non-ecc mode for the current nand flash
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* device
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+ *
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+ * @status: value to be returned if NAND_CMD_STATUS command
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+ * is executed
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+ * @use_ecc: request the controller to use ECC for the
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+ * upcoming read/write
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+ * @bch_enabled: flag to tell whether BCH ECC mode is used
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*/
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struct qcom_nand_host {
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struct nand_chip chip;
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@@ -451,12 +466,10 @@ struct qcom_nand_host {
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int cs;
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int cw_size;
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int cw_data;
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- bool use_ecc;
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- bool bch_enabled;
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int ecc_bytes_hw;
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int spare_bytes;
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int bbm_size;
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- u8 status;
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+
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int last_command;
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u32 cfg0, cfg1;
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@@ -465,23 +478,27 @@ struct qcom_nand_host {
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u32 ecc_bch_cfg;
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u32 clrflashstatus;
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u32 clrreadstatus;
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+
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+ u8 status;
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+ bool use_ecc;
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+ bool bch_enabled;
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};
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/*
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* This data type corresponds to the NAND controller properties which varies
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* among different NAND controllers.
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* @ecc_modes - ecc mode for NAND
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+ * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
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* @is_bam - whether NAND controller is using BAM
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* @is_qpic - whether NAND CTRL is part of qpic IP
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* @qpic_v2 - flag to indicate QPIC IP version 2
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- * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
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*/
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struct qcom_nandc_props {
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u32 ecc_modes;
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+ u32 dev_cmd_reg_start;
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bool is_bam;
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bool is_qpic;
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bool qpic_v2;
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- u32 dev_cmd_reg_start;
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};
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/* Frees the BAM transaction memory */
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