54 lines
2.2 KiB
Diff
54 lines
2.2 KiB
Diff
From c6b435625975d9a6daeffd81509a9877ddfb93b5 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Thu, 15 Apr 2021 13:49:56 +0300
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Subject: [PATCH 206/247] ARM: at91: sfrbu: add sfrbu registers definitions for
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sama7g5
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Add SFRBU registers definitions for SAMA7G5.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Link: https://lore.kernel.org/r/20210415105010.569620-11-claudiu.beznea@microchip.com
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---
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include/soc/at91/sama7-sfrbu.h | 34 ++++++++++++++++++++++++++++++++++
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1 file changed, 34 insertions(+)
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create mode 100644 include/soc/at91/sama7-sfrbu.h
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--- /dev/null
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+++ b/include/soc/at91/sama7-sfrbu.h
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@@ -0,0 +1,34 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+/*
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+ * Microchip SAMA7 SFRBU registers offsets and bit definitions.
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+ *
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+ * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries
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+ *
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+ * Author: Claudu Beznea <claudiu.beznea@microchip.com>
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+ */
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+
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+#ifndef __SAMA7_SFRBU_H__
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+#define __SAMA7_SFRBU_H__
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+
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+#ifdef CONFIG_SOC_SAMA7
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+
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+#define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */
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+#define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */
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+#define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */
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+#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */
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+#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */
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+
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+#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */
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+#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */
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+#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */
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+#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */
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+#define AT91_SFRBU_PD_VALUE_MSK (0x3)
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+#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */
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+
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+#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */
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+#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */
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+
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+#endif /* CONFIG_SOC_SAMA7 */
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+
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+#endif /* __SAMA7_SFRBU_H__ */
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+
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