arm-trusted-firmware-mvebu: CZ.NIC's Secure Firmware bump to v2021.09.07
bump version and remove patches that have been applied 176d701 wtmi: Wait 1s after putting PHYs INTn pin low 2eeccfe wtmi: Change comment describing reset workaround e8c94a5 wtmi: Count RAM size from both CS0 and CS1 995979e wtmi: Rename macro e29eb29 wtmi: soc: Fix start_ap_workaround() for TF-A with debug 81245ed wtmi: Use constant name PLAT_MARVELL_MAILBOX_BASE 18ccb83 wtmi: Do a proper UART reset with clock change as described in spec 15ff106 avs: Validate VDD value from OTP 3f33626 fix: clock: a3700: change pwm clock for 600/600 and 1200/750 preset fb5e436 wtmi: uart: fix UART baudrate divisor calculation Signed-off-by: sean lee <ilf@live.com>
This commit is contained in:
sean lee
Hauke Mehrtens
parent
5ef4608c02
commit
23e4d90b61
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@ -149,13 +149,13 @@ define Download/mv-ddr-marvell
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endef
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MOX_BB_NAME:=mox-boot-builder
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MOX_BB_RELEASE:=v2021.04.09
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MOX_BB_RELEASE:=v2021.09.07
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MOX_BB_SOURCE:=$(MOX_BB_NAME)-$(MOX_BB_RELEASE).tar.bz2
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define Download/mox-boot-builder
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FILE:=$(MOX_BB_SOURCE)
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URL:=https://gitlab.nic.cz/turris/mox-boot-builder/-/archive/$(MOX_BB_RELEASE)
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HASH:=f0ed4fa25006e36a07d4256f633e3f25d6f8898dbe2e081e578251a182885520
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HASH:=fd5fe276a3b0dee3177d61c017907a8eb23cd2169478fa78e9a3a836cfe3a4a8
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endef
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CM3_GCC_NAME:=gcc-arm
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@ -1,66 +0,0 @@
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From fb5e436843614f93b30aec0a2a00e5e59a133aab Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
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Date: Sat, 15 May 2021 17:44:24 +0200
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Subject: [PATCH] wtmi: uart: fix UART baudrate divisor calculation
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The UART code uses the xtal clock as parent for UART baudrate
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generation, but it assumes that xtal runs at 25 MHz, which isn't
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necessarily the case for all A3720 boards.
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Use get_ref_clk() to determine xtal clock rate.
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Use rounding division to compute the divisor value.
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Signed-off-by: Marek Behún <marek.behun@nic.cz>
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Suggested-by: Pali Rohár <pali@kernel.org>
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---
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wtmi/types.h | 5 +++++
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wtmi/uart.c | 7 ++++---
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2 files changed, 9 insertions(+), 3 deletions(-)
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diff --git a/wtmi/types.h b/wtmi/types.h
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index 7a6c6c6..ea873fc 100644
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--- a/wtmi/types.h
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+++ b/wtmi/types.h
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@@ -47,4 +47,9 @@ typedef u32 size_t;
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#define maybe_unused __attribute__((unused))
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+static inline u32 div_round_closest_u32(u32 x, u32 d)
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+{
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+ return (x + d / 2) / d;
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+}
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+
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#endif /* __TYPES_H */
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diff --git a/wtmi/uart.c b/wtmi/uart.c
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index d40633d..75864b5 100644
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--- a/wtmi/uart.c
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+++ b/wtmi/uart.c
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@@ -40,8 +40,6 @@
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#include "stdio.h"
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#include "debug.h"
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-#define UART_CLOCK_FREQ 25804800
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-
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const struct uart_info uart1_info = {
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.rx = 0xc0012000,
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.tx = 0xc0012004,
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@@ -76,8 +74,11 @@ void uart_set_stdio(const struct uart_info *info)
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void uart_reset(const struct uart_info *info, unsigned int baudrate)
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{
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+ u32 parent_rate = get_ref_clk() * 1000000;
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+
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/* set baudrate */
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- writel((UART_CLOCK_FREQ / baudrate / 16), info->baud);
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+ writel(div_round_closest_u32(parent_rate, baudrate * 16), info->baud);
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+
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/* set Programmable Oversampling Stack to 0, UART defaults to 16X scheme */
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writel(0, info->possr);
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--
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2.30.2
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@ -1,48 +0,0 @@
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From 3f33626ac7037bd62df9391e899f50e076e58cf7 Mon Sep 17 00:00:00 2001
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From: zachary <zhangzg@marvell.com>
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Date: Wed, 25 Oct 2017 15:50:29 +0800
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Subject: [PATCH] fix: clock: a3700: change pwm clock for 600/600 and 1200/750
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preset
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This patch is to change pwm clock from 100MHz to 50MHz for 600/600 and
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1200/750 preset to align with other presets.
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Change-Id: I067e189043be8c776bd3e7015a06f8ddf2590b96
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Signed-off-by: zachary <zhangzg@marvell.com>
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Reviewed-on: http://vgitil04.il.marvell.com:8080/45513
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Tested-by: iSoC Platform CI <ykjenk@marvell.com>
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Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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Reviewed-by: Hua Jing <jinghua@marvell.com>
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Signed-off-by: Marek Behún <marek.behun@nic.cz>
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---
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wtmi/clock.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/wtmi/clock.c b/wtmi/clock.c
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index 97c2825..1a1f0c6 100644
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--- a/wtmi/clock.c
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+++ b/wtmi/clock.c
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@@ -447,7 +447,7 @@ static struct clock_cfg clk_cfg_all[] = {\
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/* NorthBridge */\
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{{TBG_A_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_A_P, TBG_A_P, TBG_A_P,\
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TBG_B_S, TBG_B_S, TBG_A_P, TBG_B_S, TBG_A_P, TBG_B_S},\
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- {2, 5, 2, 4, 1, 2, 6, 2}, /* DIV0 */\
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+ {4, 5, 2, 4, 1, 2, 6, 2}, /* DIV0 */\
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{1, 5, 2, 5, 2, 3, 2, 2, 3}, /* DIV1 */\
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{4, 1, 5, 1, 3, 1, 2, 0, 0, 1} }, /* DIV2 */\
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/* SouthBridge */\
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@@ -495,7 +495,7 @@ static struct clock_cfg clk_cfg_all[] = {\
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/* NorthBridge */\
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{{TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S,\
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TBG_B_S, TBG_A_S, TBG_B_S, TBG_A_P, TBG_B_S, TBG_A_S},\
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- {3, 4, 3, 4, 1, 1, 5, 1}, /* DIV0 */\
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+ {6, 4, 3, 4, 1, 1, 5, 1}, /* DIV0 */\
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{1, 6, 3, 4, 1, 6, 1, 1, 6}, /* DIV1 */\
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{4, 1, 6, 1, 3, 1, 3, 0, 0, 1} }, /* DIV2 */\
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/* SouthBridge */\
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--
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2.30.2
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@ -1,52 +0,0 @@
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From 15ff10623c83ee2e626d93d16e022b115dcb608f Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Sat, 10 Apr 2021 16:56:12 +0200
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Subject: [PATCH] avs: Validate VDD value from OTP
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CPU VDD voltage value for 1.2 GHz frequency on some Espressobin boards is
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not set and raw value 0x00 is returned. In this case init_avs() function
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calculated CPU VDD voltage value to 0x00 + AVS_VDD_BASE = 0.898 V, which is
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too low for any operation and Espressobin board immediately crashed
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init_avs() function set this low value.
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This patch fixes above issue by validating returned VDD value from OTP and
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using default VDD value when invalid value is in OTP. With this patch
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init_avs() function does cause CPU crash anymore.
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <marek.behun@nic.cz>
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---
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wtmi/avs.c | 14 ++++++++++----
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1 file changed, 10 insertions(+), 4 deletions(-)
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diff --git a/wtmi/avs.c b/wtmi/avs.c
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index 36ca9fa..4624359 100644
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--- a/wtmi/avs.c
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+++ b/wtmi/avs.c
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@@ -140,10 +140,16 @@ int init_avs(u32 speed)
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}
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if (svc_rev >= SVC_REVISION_2) {
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- vdd_otp = ((otp_data[OTP_DATA_SVC_SPEED_ID] >> shift) +
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- AVS_VDD_BASE) & AVS_VDD_MASK;
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- regval |= (vdd_otp << HIGH_VDD_LIMIT_OFF);
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- regval |= (vdd_otp << LOW_VDD_LIMIT_OFF);
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+ vdd_otp = (otp_data[OTP_DATA_SVC_SPEED_ID] >> shift) &
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+ AVS_VDD_MASK;
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+ if (!vdd_otp || vdd_otp + AVS_VDD_BASE > AVS_VDD_MASK) {
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+ regval |= (vdd_default << HIGH_VDD_LIMIT_OFF);
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+ regval |= (vdd_default << LOW_VDD_LIMIT_OFF);
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+ } else {
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+ vdd_otp += AVS_VDD_BASE;
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+ regval |= (vdd_otp << HIGH_VDD_LIMIT_OFF);
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+ regval |= (vdd_otp << LOW_VDD_LIMIT_OFF);
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+ }
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} else {
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regval |= (vdd_default << HIGH_VDD_LIMIT_OFF);
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regval |= (vdd_default << LOW_VDD_LIMIT_OFF);
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--
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2.30.2
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