Merge Official Source
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
commit
52e0fddb99
|
@ -80,7 +80,8 @@ mercusys,mr90x-v1)
|
|||
cetron,ct3003-stock|\
|
||||
cetron,ct3003-ubootmod|\
|
||||
cmcc,rax3000m-nand-ubootmod|\
|
||||
netgear,wax220)
|
||||
netgear,wax220|\
|
||||
zbtlink,zbt-z8102ax)
|
||||
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000"
|
||||
;;
|
||||
ubnt,unifi-6-plus)
|
||||
|
|
|
@ -170,6 +170,13 @@ define Package/iwlwifi-firmware-iwl9260/install
|
|||
endef
|
||||
$(eval $(call BuildPackage,iwlwifi-firmware-iwl9260))
|
||||
|
||||
Package/iwlwifi-firmware-ax101 = $(call Package/firmware-default,Intel AX101 firmware)
|
||||
define Package/iwlwifi-firmware-ax101/install
|
||||
$(INSTALL_DIR) $(1)/lib/firmware
|
||||
$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-so-a0-hr-b0-81.ucode $(1)/lib/firmware
|
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endef
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$(eval $(call BuildPackage,iwlwifi-firmware-ax101))
|
||||
|
||||
Package/iwlwifi-firmware-ax200 = $(call Package/firmware-default,Intel AX200 firmware)
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define Package/iwlwifi-firmware-ax200/install
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$(INSTALL_DIR) $(1)/lib/firmware
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|
|
|
@ -378,9 +378,11 @@ $(eval $(call KernelPackage,phy-smsc))
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define KernelPackage/phy-aquantia
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SUBMENU:=$(NETWORK_DEVICES_MENU)
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TITLE:=Aquantia Ethernet PHYs
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DEPENDS:=+kmod-libphy +kmod-hwmon-core
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DEPENDS:=+kmod-libphy +kmod-hwmon-core +kmod-lib-crc-ccitt
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KCONFIG:=CONFIG_AQUANTIA_PHY
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FILES:=$(LINUX_DIR)/drivers/net/phy/aquantia.ko
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FILES:= \
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$(LINUX_DIR)/drivers/net/phy/aquantia.ko@lt6.1 \
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$(LINUX_DIR)/drivers/net/phy/aquantia/aquantia.ko@ge6.1
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AUTOLOAD:=$(call AutoLoad,18,aquantia,1)
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endef
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||||
|
||||
|
|
|
@ -34,7 +34,7 @@ def get_pid(args):
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|||
enc = args.hw_version.rjust(8, '0').encode('ascii')
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struct.pack_into('>8s', buf, 0x0, enc)
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enc = binascii.hexlify(args.hw_id.encode())
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enc = binascii.hexlify(args.hw_id.encode()).upper()
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struct.pack_into('>6s', buf, 0x8, enc)
|
||||
|
||||
enc = args.sw_version.rjust(4, '0').encode('ascii')
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||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,183 @@
|
|||
From e1fbfa4a995d42e02e22b0dff2f8b4fdee1504b3 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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||||
Date: Tue, 14 Nov 2023 15:08:42 +0100
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||||
Subject: [PATCH 2/3] net: phy: aquantia: move MMD_VEND define to header
|
||||
|
||||
Move MMD_VEND define to header to clean things up and in preparation for
|
||||
firmware loading support that require some define placed in
|
||||
aquantia_main.
|
||||
|
||||
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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||||
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
drivers/net/phy/aquantia/aquantia.h | 69 +++++++++++++++++++++++
|
||||
drivers/net/phy/aquantia/aquantia_hwmon.c | 14 -----
|
||||
drivers/net/phy/aquantia/aquantia_main.c | 55 ------------------
|
||||
3 files changed, 69 insertions(+), 69 deletions(-)
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|
||||
--- a/drivers/net/phy/aquantia/aquantia.h
|
||||
+++ b/drivers/net/phy/aquantia/aquantia.h
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||||
@@ -9,6 +9,75 @@
|
||||
#include <linux/device.h>
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||||
#include <linux/phy.h>
|
||||
|
||||
+/* Vendor specific 1, MDIO_MMD_VEND1 */
|
||||
+#define VEND1_GLOBAL_FW_ID 0x0020
|
||||
+#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
|
||||
+#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
|
||||
+
|
||||
+/* The following registers all have similar layouts; first the registers... */
|
||||
+#define VEND1_GLOBAL_CFG_10M 0x0310
|
||||
+#define VEND1_GLOBAL_CFG_100M 0x031b
|
||||
+#define VEND1_GLOBAL_CFG_1G 0x031c
|
||||
+#define VEND1_GLOBAL_CFG_2_5G 0x031d
|
||||
+#define VEND1_GLOBAL_CFG_5G 0x031e
|
||||
+#define VEND1_GLOBAL_CFG_10G 0x031f
|
||||
+/* ...and now the fields */
|
||||
+#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
|
||||
+#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
|
||||
+#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
|
||||
+#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
|
||||
+
|
||||
+/* Vendor specific 1, MDIO_MMD_VEND2 */
|
||||
+#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
|
||||
+#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
|
||||
+#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
|
||||
+#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
|
||||
+#define VEND1_THERMAL_STAT1 0xc820
|
||||
+#define VEND1_THERMAL_STAT2 0xc821
|
||||
+#define VEND1_THERMAL_STAT2_VALID BIT(0)
|
||||
+#define VEND1_GENERAL_STAT1 0xc830
|
||||
+#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
|
||||
+#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
|
||||
+#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
|
||||
+#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
|
||||
+
|
||||
+#define VEND1_GLOBAL_GEN_STAT2 0xc831
|
||||
+#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
|
||||
+
|
||||
+#define VEND1_GLOBAL_RSVD_STAT1 0xc885
|
||||
+#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
|
||||
+#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
|
||||
+
|
||||
+#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
|
||||
+#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
|
||||
+#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
|
||||
+
|
||||
+#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
|
||||
+#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
|
||||
+
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK 0xff00
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
|
||||
+#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
|
||||
+
|
||||
+#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
|
||||
+#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
|
||||
+#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
|
||||
+#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
|
||||
+#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
|
||||
+#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
|
||||
+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
|
||||
+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
|
||||
+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
|
||||
+
|
||||
#if IS_REACHABLE(CONFIG_HWMON)
|
||||
int aqr_hwmon_probe(struct phy_device *phydev);
|
||||
#else
|
||||
--- a/drivers/net/phy/aquantia/aquantia_hwmon.c
|
||||
+++ b/drivers/net/phy/aquantia/aquantia_hwmon.c
|
||||
@@ -13,20 +13,6 @@
|
||||
|
||||
#include "aquantia.h"
|
||||
|
||||
-/* Vendor specific 1, MDIO_MMD_VEND2 */
|
||||
-#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
|
||||
-#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
|
||||
-#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
|
||||
-#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
|
||||
-#define VEND1_THERMAL_STAT1 0xc820
|
||||
-#define VEND1_THERMAL_STAT2 0xc821
|
||||
-#define VEND1_THERMAL_STAT2_VALID BIT(0)
|
||||
-#define VEND1_GENERAL_STAT1 0xc830
|
||||
-#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
|
||||
-#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
|
||||
-#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
|
||||
-#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
|
||||
-
|
||||
#if IS_REACHABLE(CONFIG_HWMON)
|
||||
|
||||
static umode_t aqr_hwmon_is_visible(const void *data,
|
||||
--- a/drivers/net/phy/aquantia/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia/aquantia_main.c
|
||||
@@ -89,61 +89,6 @@
|
||||
#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
|
||||
#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
|
||||
|
||||
-/* Vendor specific 1, MDIO_MMD_VEND1 */
|
||||
-#define VEND1_GLOBAL_FW_ID 0x0020
|
||||
-#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
|
||||
-#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
|
||||
-
|
||||
-#define VEND1_GLOBAL_GEN_STAT2 0xc831
|
||||
-#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
|
||||
-
|
||||
-/* The following registers all have similar layouts; first the registers... */
|
||||
-#define VEND1_GLOBAL_CFG_10M 0x0310
|
||||
-#define VEND1_GLOBAL_CFG_100M 0x031b
|
||||
-#define VEND1_GLOBAL_CFG_1G 0x031c
|
||||
-#define VEND1_GLOBAL_CFG_2_5G 0x031d
|
||||
-#define VEND1_GLOBAL_CFG_5G 0x031e
|
||||
-#define VEND1_GLOBAL_CFG_10G 0x031f
|
||||
-/* ...and now the fields */
|
||||
-#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
|
||||
-#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
|
||||
-#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
|
||||
-#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
|
||||
-
|
||||
-#define VEND1_GLOBAL_RSVD_STAT1 0xc885
|
||||
-#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
|
||||
-#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
|
||||
-
|
||||
-#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
|
||||
-#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
|
||||
-#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
|
||||
-
|
||||
-#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
|
||||
-#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
|
||||
-
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK 0xff00
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
|
||||
-#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
|
||||
-
|
||||
-#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
|
||||
-#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
|
||||
-#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
|
||||
-#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
|
||||
-#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
|
||||
-#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
|
||||
-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
|
||||
-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
|
||||
-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
|
||||
-
|
||||
/* Sleep and timeout for checking if the Processor-Intensive
|
||||
* MDIO operation is finished
|
||||
*/
|
|
@ -0,0 +1,504 @@
|
|||
From e93984ebc1c82bd34f7a1b3391efaceee0a8ae96 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Tue, 14 Nov 2023 15:08:43 +0100
|
||||
Subject: [PATCH 3/3] net: phy: aquantia: add firmware load support
|
||||
|
||||
Aquantia PHY-s require firmware to be loaded before they start operating.
|
||||
It can be automatically loaded in case when there is a SPI-NOR connected
|
||||
to Aquantia PHY-s or can be loaded from the host via MDIO.
|
||||
|
||||
This patch adds support for loading the firmware via MDIO as in most cases
|
||||
there is no SPI-NOR being used to save on cost.
|
||||
Firmware loading code itself is ported from mainline U-boot with cleanups.
|
||||
|
||||
The firmware has mixed values both in big and little endian.
|
||||
PHY core itself is big-endian but it expects values to be in little-endian.
|
||||
The firmware is little-endian but CRC-16 value for it is stored at the end
|
||||
of firmware in big-endian.
|
||||
|
||||
It seems the PHY does the conversion internally from firmware that is
|
||||
little-endian to the PHY that is big-endian on using the mailbox
|
||||
but mailbox returns a big-endian CRC-16 to verify the written data
|
||||
integrity.
|
||||
|
||||
Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
||||
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
drivers/net/phy/aquantia/Kconfig | 1 +
|
||||
drivers/net/phy/aquantia/Makefile | 2 +-
|
||||
drivers/net/phy/aquantia/aquantia.h | 32 ++
|
||||
drivers/net/phy/aquantia/aquantia_firmware.c | 370 +++++++++++++++++++
|
||||
drivers/net/phy/aquantia/aquantia_main.c | 6 +
|
||||
5 files changed, 410 insertions(+), 1 deletion(-)
|
||||
create mode 100644 drivers/net/phy/aquantia/aquantia_firmware.c
|
||||
|
||||
--- a/drivers/net/phy/aquantia/Kconfig
|
||||
+++ b/drivers/net/phy/aquantia/Kconfig
|
||||
@@ -1,5 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
config AQUANTIA_PHY
|
||||
tristate "Aquantia PHYs"
|
||||
+ select CRC_CCITT
|
||||
help
|
||||
Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
|
||||
--- a/drivers/net/phy/aquantia/Makefile
|
||||
+++ b/drivers/net/phy/aquantia/Makefile
|
||||
@@ -1,5 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
-aquantia-objs += aquantia_main.o
|
||||
+aquantia-objs += aquantia_main.o aquantia_firmware.o
|
||||
ifdef CONFIG_HWMON
|
||||
aquantia-objs += aquantia_hwmon.o
|
||||
endif
|
||||
--- a/drivers/net/phy/aquantia/aquantia.h
|
||||
+++ b/drivers/net/phy/aquantia/aquantia.h
|
||||
@@ -10,10 +10,35 @@
|
||||
#include <linux/phy.h>
|
||||
|
||||
/* Vendor specific 1, MDIO_MMD_VEND1 */
|
||||
+#define VEND1_GLOBAL_SC 0x0
|
||||
+#define VEND1_GLOBAL_SC_SOFT_RESET BIT(15)
|
||||
+#define VEND1_GLOBAL_SC_LOW_POWER BIT(11)
|
||||
+
|
||||
#define VEND1_GLOBAL_FW_ID 0x0020
|
||||
#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
|
||||
#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
|
||||
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE1 0x0200
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE BIT(15)
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE BIT(14)
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET BIT(12)
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE1_BUSY BIT(8)
|
||||
+
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE2 0x0201
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE3 0x0202
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK GENMASK(15, 0)
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK, (u16)((x) >> 16))
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE4 0x0203
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK GENMASK(15, 2)
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK, (u16)(x))
|
||||
+
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE5 0x0204
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK GENMASK(15, 0)
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK, (u16)((x) >> 16))
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE6 0x0205
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK GENMASK(15, 0)
|
||||
+#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK, (u16)(x))
|
||||
+
|
||||
/* The following registers all have similar layouts; first the registers... */
|
||||
#define VEND1_GLOBAL_CFG_10M 0x0310
|
||||
#define VEND1_GLOBAL_CFG_100M 0x031b
|
||||
@@ -28,6 +53,11 @@
|
||||
#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
|
||||
|
||||
/* Vendor specific 1, MDIO_MMD_VEND2 */
|
||||
+#define VEND1_GLOBAL_CONTROL2 0xc001
|
||||
+#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST BIT(15)
|
||||
+#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD BIT(6)
|
||||
+#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL BIT(0)
|
||||
+
|
||||
#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
|
||||
#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
|
||||
#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
|
||||
@@ -83,3 +113,5 @@ int aqr_hwmon_probe(struct phy_device *p
|
||||
#else
|
||||
static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
|
||||
#endif
|
||||
+
|
||||
+int aqr_firmware_load(struct phy_device *phydev);
|
||||
--- /dev/null
|
||||
+++ b/drivers/net/phy/aquantia/aquantia_firmware.c
|
||||
@@ -0,0 +1,370 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+
|
||||
+#include <linux/bitfield.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/firmware.h>
|
||||
+#include <linux/crc-ccitt.h>
|
||||
+#include <linux/nvmem-consumer.h>
|
||||
+
|
||||
+#include <asm/unaligned.h>
|
||||
+
|
||||
+#include "aquantia.h"
|
||||
+
|
||||
+#define UP_RESET_SLEEP 100
|
||||
+
|
||||
+/* addresses of memory segments in the phy */
|
||||
+#define DRAM_BASE_ADDR 0x3FFE0000
|
||||
+#define IRAM_BASE_ADDR 0x40000000
|
||||
+
|
||||
+/* firmware image format constants */
|
||||
+#define VERSION_STRING_SIZE 0x40
|
||||
+#define VERSION_STRING_OFFSET 0x0200
|
||||
+/* primary offset is written at an offset from the start of the fw blob */
|
||||
+#define PRIMARY_OFFSET_OFFSET 0x8
|
||||
+/* primary offset needs to be then added to a base offset */
|
||||
+#define PRIMARY_OFFSET_SHIFT 12
|
||||
+#define PRIMARY_OFFSET(x) ((x) << PRIMARY_OFFSET_SHIFT)
|
||||
+#define HEADER_OFFSET 0x300
|
||||
+
|
||||
+struct aqr_fw_header {
|
||||
+ u32 padding;
|
||||
+ u8 iram_offset[3];
|
||||
+ u8 iram_size[3];
|
||||
+ u8 dram_offset[3];
|
||||
+ u8 dram_size[3];
|
||||
+} __packed;
|
||||
+
|
||||
+enum aqr_fw_src {
|
||||
+ AQR_FW_SRC_NVMEM = 0,
|
||||
+ AQR_FW_SRC_FS,
|
||||
+};
|
||||
+
|
||||
+static const char * const aqr_fw_src_string[] = {
|
||||
+ [AQR_FW_SRC_NVMEM] = "NVMEM",
|
||||
+ [AQR_FW_SRC_FS] = "FS",
|
||||
+};
|
||||
+
|
||||
+/* AQR firmware doesn't have fixed offsets for iram and dram section
|
||||
+ * but instead provide an header with the offset to use on reading
|
||||
+ * and parsing the firmware.
|
||||
+ *
|
||||
+ * AQR firmware can't be trusted and each offset is validated to be
|
||||
+ * not negative and be in the size of the firmware itself.
|
||||
+ */
|
||||
+static bool aqr_fw_validate_get(size_t size, size_t offset, size_t get_size)
|
||||
+{
|
||||
+ return offset + get_size <= size;
|
||||
+}
|
||||
+
|
||||
+static int aqr_fw_get_be16(const u8 *data, size_t offset, size_t size, u16 *value)
|
||||
+{
|
||||
+ if (!aqr_fw_validate_get(size, offset, sizeof(u16)))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ *value = get_unaligned_be16(data + offset);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int aqr_fw_get_le16(const u8 *data, size_t offset, size_t size, u16 *value)
|
||||
+{
|
||||
+ if (!aqr_fw_validate_get(size, offset, sizeof(u16)))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ *value = get_unaligned_le16(data + offset);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int aqr_fw_get_le24(const u8 *data, size_t offset, size_t size, u32 *value)
|
||||
+{
|
||||
+ if (!aqr_fw_validate_get(size, offset, sizeof(u8) * 3))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ *value = get_unaligned_le24(data + offset);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/* load data into the phy's memory */
|
||||
+static int aqr_fw_load_memory(struct phy_device *phydev, u32 addr,
|
||||
+ const u8 *data, size_t len)
|
||||
+{
|
||||
+ u16 crc = 0, up_crc;
|
||||
+ size_t pos;
|
||||
+
|
||||
+ /* PHY expect addr in LE */
|
||||
+ addr = (__force u32)cpu_to_le32(addr);
|
||||
+
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
|
||||
+ VEND1_GLOBAL_MAILBOX_INTERFACE1,
|
||||
+ VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET);
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
|
||||
+ VEND1_GLOBAL_MAILBOX_INTERFACE3,
|
||||
+ VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(addr));
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
|
||||
+ VEND1_GLOBAL_MAILBOX_INTERFACE4,
|
||||
+ VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(addr));
|
||||
+
|
||||
+ /* We assume and enforce the size to be word aligned.
|
||||
+ * If a firmware that is not word aligned is found, please report upstream.
|
||||
+ */
|
||||
+ for (pos = 0; pos < len; pos += sizeof(u32)) {
|
||||
+ u32 word;
|
||||
+
|
||||
+ /* FW data is always stored in little-endian */
|
||||
+ word = get_unaligned((const u32 *)(data + pos));
|
||||
+
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5,
|
||||
+ VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(word));
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE6,
|
||||
+ VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(word));
|
||||
+
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE1,
|
||||
+ VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE |
|
||||
+ VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE);
|
||||
+
|
||||
+ /* calculate CRC as we load data to the mailbox.
|
||||
+ * We convert word to big-endian as PHY is BE and mailbox will
|
||||
+ * return a BE CRC.
|
||||
+ */
|
||||
+ word = (__force u32)cpu_to_be32(word);
|
||||
+ crc = crc_ccitt_false(crc, (u8 *)&word, sizeof(word));
|
||||
+ }
|
||||
+
|
||||
+ up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE2);
|
||||
+ if (crc != up_crc) {
|
||||
+ phydev_err(phydev, "CRC mismatch: calculated 0x%04x PHY 0x%04x\n",
|
||||
+ crc, up_crc);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int aqr_fw_boot(struct phy_device *phydev, const u8 *data, size_t size,
|
||||
+ enum aqr_fw_src fw_src)
|
||||
+{
|
||||
+ u16 calculated_crc, read_crc, read_primary_offset;
|
||||
+ u32 iram_offset = 0, iram_size = 0;
|
||||
+ u32 dram_offset = 0, dram_size = 0;
|
||||
+ char version[VERSION_STRING_SIZE];
|
||||
+ u32 primary_offset = 0;
|
||||
+ int ret;
|
||||
+
|
||||
+ /* extract saved CRC at the end of the fw
|
||||
+ * CRC is saved in big-endian as PHY is BE
|
||||
+ */
|
||||
+ ret = aqr_fw_get_be16(data, size - sizeof(u16), size, &read_crc);
|
||||
+ if (ret) {
|
||||
+ phydev_err(phydev, "bad firmware CRC in firmware\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ calculated_crc = crc_ccitt_false(0, data, size - sizeof(u16));
|
||||
+ if (read_crc != calculated_crc) {
|
||||
+ phydev_err(phydev, "bad firmware CRC: file 0x%04x calculated 0x%04x\n",
|
||||
+ read_crc, calculated_crc);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ /* Get the primary offset to extract DRAM and IRAM sections. */
|
||||
+ ret = aqr_fw_get_le16(data, PRIMARY_OFFSET_OFFSET, size, &read_primary_offset);
|
||||
+ if (ret) {
|
||||
+ phydev_err(phydev, "bad primary offset in firmware\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ primary_offset = PRIMARY_OFFSET(read_primary_offset);
|
||||
+
|
||||
+ /* Find the DRAM and IRAM sections within the firmware file.
|
||||
+ * Make sure the fw_header is correctly in the firmware.
|
||||
+ */
|
||||
+ if (!aqr_fw_validate_get(size, primary_offset + HEADER_OFFSET,
|
||||
+ sizeof(struct aqr_fw_header))) {
|
||||
+ phydev_err(phydev, "bad fw_header in firmware\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ /* offset are in LE and values needs to be converted to cpu endian */
|
||||
+ ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
|
||||
+ offsetof(struct aqr_fw_header, iram_offset),
|
||||
+ size, &iram_offset);
|
||||
+ if (ret) {
|
||||
+ phydev_err(phydev, "bad iram offset in firmware\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
|
||||
+ offsetof(struct aqr_fw_header, iram_size),
|
||||
+ size, &iram_size);
|
||||
+ if (ret) {
|
||||
+ phydev_err(phydev, "invalid iram size in firmware\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
|
||||
+ offsetof(struct aqr_fw_header, dram_offset),
|
||||
+ size, &dram_offset);
|
||||
+ if (ret) {
|
||||
+ phydev_err(phydev, "bad dram offset in firmware\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
|
||||
+ offsetof(struct aqr_fw_header, dram_size),
|
||||
+ size, &dram_size);
|
||||
+ if (ret) {
|
||||
+ phydev_err(phydev, "invalid dram size in firmware\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* Increment the offset with the primary offset.
|
||||
+ * Validate iram/dram offset and size.
|
||||
+ */
|
||||
+ iram_offset += primary_offset;
|
||||
+ if (iram_size % sizeof(u32)) {
|
||||
+ phydev_err(phydev, "iram size if not aligned to word size. Please report this upstream!\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ if (!aqr_fw_validate_get(size, iram_offset, iram_size)) {
|
||||
+ phydev_err(phydev, "invalid iram offset for iram size\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ dram_offset += primary_offset;
|
||||
+ if (dram_size % sizeof(u32)) {
|
||||
+ phydev_err(phydev, "dram size if not aligned to word size. Please report this upstream!\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ if (!aqr_fw_validate_get(size, dram_offset, dram_size)) {
|
||||
+ phydev_err(phydev, "invalid iram offset for iram size\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ phydev_dbg(phydev, "primary %d IRAM offset=%d size=%d DRAM offset=%d size=%d\n",
|
||||
+ primary_offset, iram_offset, iram_size, dram_offset, dram_size);
|
||||
+
|
||||
+ if (!aqr_fw_validate_get(size, dram_offset + VERSION_STRING_OFFSET,
|
||||
+ VERSION_STRING_SIZE)) {
|
||||
+ phydev_err(phydev, "invalid version in firmware\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ strscpy(version, (char *)data + dram_offset + VERSION_STRING_OFFSET,
|
||||
+ VERSION_STRING_SIZE);
|
||||
+ if (version[0] == '\0') {
|
||||
+ phydev_err(phydev, "invalid version in firmware\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ phydev_info(phydev, "loading firmware version '%s' from '%s'\n", version,
|
||||
+ aqr_fw_src_string[fw_src]);
|
||||
+
|
||||
+ /* stall the microcprocessor */
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
|
||||
+ VEND1_GLOBAL_CONTROL2_UP_RUN_STALL | VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD);
|
||||
+
|
||||
+ phydev_dbg(phydev, "loading DRAM 0x%08x from offset=%d size=%d\n",
|
||||
+ DRAM_BASE_ADDR, dram_offset, dram_size);
|
||||
+ ret = aqr_fw_load_memory(phydev, DRAM_BASE_ADDR, data + dram_offset,
|
||||
+ dram_size);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ phydev_dbg(phydev, "loading IRAM 0x%08x from offset=%d size=%d\n",
|
||||
+ IRAM_BASE_ADDR, iram_offset, iram_size);
|
||||
+ ret = aqr_fw_load_memory(phydev, IRAM_BASE_ADDR, data + iram_offset,
|
||||
+ iram_size);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* make sure soft reset and low power mode are clear */
|
||||
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SC,
|
||||
+ VEND1_GLOBAL_SC_SOFT_RESET | VEND1_GLOBAL_SC_LOW_POWER);
|
||||
+
|
||||
+ /* Release the microprocessor. UP_RESET must be held for 100 usec. */
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
|
||||
+ VEND1_GLOBAL_CONTROL2_UP_RUN_STALL |
|
||||
+ VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD |
|
||||
+ VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST);
|
||||
+ usleep_range(UP_RESET_SLEEP, UP_RESET_SLEEP * 2);
|
||||
+
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
|
||||
+ VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int aqr_firmware_load_nvmem(struct phy_device *phydev)
|
||||
+{
|
||||
+ struct nvmem_cell *cell;
|
||||
+ size_t size;
|
||||
+ u8 *buf;
|
||||
+ int ret;
|
||||
+
|
||||
+ cell = nvmem_cell_get(&phydev->mdio.dev, "firmware");
|
||||
+ if (IS_ERR(cell))
|
||||
+ return PTR_ERR(cell);
|
||||
+
|
||||
+ buf = nvmem_cell_read(cell, &size);
|
||||
+ if (IS_ERR(buf)) {
|
||||
+ ret = PTR_ERR(buf);
|
||||
+ goto exit;
|
||||
+ }
|
||||
+
|
||||
+ ret = aqr_fw_boot(phydev, buf, size, AQR_FW_SRC_NVMEM);
|
||||
+ if (ret)
|
||||
+ phydev_err(phydev, "firmware loading failed: %d\n", ret);
|
||||
+
|
||||
+ kfree(buf);
|
||||
+exit:
|
||||
+ nvmem_cell_put(cell);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int aqr_firmware_load_fs(struct phy_device *phydev)
|
||||
+{
|
||||
+ struct device *dev = &phydev->mdio.dev;
|
||||
+ const struct firmware *fw;
|
||||
+ const char *fw_name;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = of_property_read_string(dev->of_node, "firmware-name",
|
||||
+ &fw_name);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = request_firmware(&fw, fw_name, dev);
|
||||
+ if (ret) {
|
||||
+ phydev_err(phydev, "failed to find FW file %s (%d)\n",
|
||||
+ fw_name, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = aqr_fw_boot(phydev, fw->data, fw->size, AQR_FW_SRC_FS);
|
||||
+ if (ret)
|
||||
+ phydev_err(phydev, "firmware loading failed: %d\n", ret);
|
||||
+
|
||||
+ release_firmware(fw);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+int aqr_firmware_load(struct phy_device *phydev)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ /* Check if the firmware is not already loaded by pooling
|
||||
+ * the current version returned by the PHY. If 0 is returned,
|
||||
+ * no firmware is loaded.
|
||||
+ */
|
||||
+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
|
||||
+ if (ret > 0)
|
||||
+ goto exit;
|
||||
+
|
||||
+ ret = aqr_firmware_load_nvmem(phydev);
|
||||
+ if (!ret)
|
||||
+ goto exit;
|
||||
+
|
||||
+ ret = aqr_firmware_load_fs(phydev);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+exit:
|
||||
+ return 0;
|
||||
+}
|
||||
--- a/drivers/net/phy/aquantia/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia/aquantia_main.c
|
||||
@@ -656,11 +656,17 @@ static int aqr107_resume(struct phy_devi
|
||||
|
||||
static int aqr107_probe(struct phy_device *phydev)
|
||||
{
|
||||
+ int ret;
|
||||
+
|
||||
phydev->priv = devm_kzalloc(&phydev->mdio.dev,
|
||||
sizeof(struct aqr107_priv), GFP_KERNEL);
|
||||
if (!phydev->priv)
|
||||
return -ENOMEM;
|
||||
|
||||
+ ret = aqr_firmware_load(phydev);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
return aqr_hwmon_probe(phydev);
|
||||
}
|
||||
|
|
@ -31,7 +31,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
|
|||
F: drivers/net/phy/motorcomm.c
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -260,7 +260,7 @@ config MOTORCOMM_PHY
|
||||
@@ -257,7 +257,7 @@ config MOTORCOMM_PHY
|
||||
tristate "Motorcomm PHYs"
|
||||
help
|
||||
Enables support for Motorcomm network PHYs.
|
||||
|
|
|
@ -22,7 +22,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
|
|||
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -260,7 +260,7 @@ config MOTORCOMM_PHY
|
||||
@@ -257,7 +257,7 @@ config MOTORCOMM_PHY
|
||||
tristate "Motorcomm PHYs"
|
||||
help
|
||||
Enables support for Motorcomm network PHYs.
|
||||
|
|
|
@ -19,7 +19,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
|
|||
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -260,7 +260,7 @@ config MOTORCOMM_PHY
|
||||
@@ -257,7 +257,7 @@ config MOTORCOMM_PHY
|
||||
tristate "Motorcomm PHYs"
|
||||
help
|
||||
Enables support for Motorcomm network PHYs.
|
||||
|
|
|
@ -7,8 +7,8 @@ PHYs AQR113C and AQR813.
|
|||
|
||||
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
|
||||
|
||||
--- a/drivers/net/phy/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia_main.c
|
||||
--- a/drivers/net/phy/aquantia/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia/aquantia_main.c
|
||||
@@ -23,6 +23,7 @@
|
||||
#define PHY_ID_AQCS109 0x03a1b5c2
|
||||
#define PHY_ID_AQR405 0x03a1b4b0
|
||||
|
@ -17,7 +17,7 @@ Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
|
|||
|
||||
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
|
||||
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
|
||||
@@ -415,6 +416,49 @@ static int aqr107_read_rate(struct phy_d
|
||||
@@ -360,6 +361,49 @@ static int aqr107_read_rate(struct phy_d
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -67,7 +67,7 @@ Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
|
|||
static int aqr107_read_status(struct phy_device *phydev)
|
||||
{
|
||||
int val, ret;
|
||||
@@ -554,7 +598,7 @@ static void aqr107_chip_info(struct phy_
|
||||
@@ -499,7 +543,7 @@ static void aqr107_chip_info(struct phy_
|
||||
build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
|
||||
prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
|
||||
|
||||
|
@ -76,7 +76,7 @@ Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
|
|||
fw_major, fw_minor, build_id, prov_id);
|
||||
}
|
||||
|
||||
@@ -809,7 +853,7 @@ static struct phy_driver aqr_driver[] =
|
||||
@@ -760,7 +804,7 @@ static struct phy_driver aqr_driver[] =
|
||||
.config_aneg = aqr_config_aneg,
|
||||
.config_intr = aqr_config_intr,
|
||||
.handle_interrupt = aqr_handle_interrupt,
|
||||
|
@ -85,7 +85,7 @@ Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
|
|||
.get_tunable = aqr107_get_tunable,
|
||||
.set_tunable = aqr107_set_tunable,
|
||||
.suspend = aqr107_suspend,
|
||||
@@ -819,6 +863,24 @@ static struct phy_driver aqr_driver[] =
|
||||
@@ -770,6 +814,24 @@ static struct phy_driver aqr_driver[] =
|
||||
.get_stats = aqr107_get_stats,
|
||||
.link_change_notify = aqr107_link_change_notify,
|
||||
},
|
||||
|
@ -110,7 +110,7 @@ Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
|
|||
};
|
||||
|
||||
module_phy_driver(aqr_driver);
|
||||
@@ -832,6 +894,7 @@ static struct mdio_device_id __maybe_unu
|
||||
@@ -783,6 +845,7 @@ static struct mdio_device_id __maybe_unu
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
|
||||
|
|
|
@ -10,11 +10,11 @@ different firmware on the PHY.
|
|||
|
||||
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
|
||||
---
|
||||
drivers/net/phy/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++
|
||||
drivers/net/phy/aquantia/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 88 insertions(+)
|
||||
|
||||
--- a/drivers/net/phy/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia_main.c
|
||||
--- a/drivers/net/phy/aquantia/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia/aquantia_main.c
|
||||
@@ -24,6 +24,8 @@
|
||||
#define PHY_ID_AQR405 0x03a1b4b0
|
||||
#define PHY_ID_AQR113C 0x31c31c12
|
||||
|
@ -24,7 +24,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
|
|||
|
||||
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
|
||||
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
|
||||
@@ -151,6 +153,29 @@
|
||||
@@ -96,6 +98,29 @@
|
||||
#define AQR107_OP_IN_PROG_SLEEP 1000
|
||||
#define AQR107_OP_IN_PROG_TIMEOUT 100000
|
||||
|
||||
|
@ -54,7 +54,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
|
|||
struct aqr107_hw_stat {
|
||||
const char *name;
|
||||
int reg;
|
||||
@@ -282,6 +307,51 @@ static int aqr_config_aneg(struct phy_de
|
||||
@@ -227,6 +252,51 @@ static int aqr_config_aneg(struct phy_de
|
||||
return genphy_c45_check_and_restart_aneg(phydev, changed);
|
||||
}
|
||||
|
||||
|
@ -106,7 +106,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
|
|||
static int aqr_config_intr(struct phy_device *phydev)
|
||||
{
|
||||
bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
|
||||
@@ -881,6 +951,30 @@ static struct phy_driver aqr_driver[] =
|
||||
@@ -832,6 +902,30 @@ static struct phy_driver aqr_driver[] =
|
||||
.get_stats = aqr107_get_stats,
|
||||
.link_change_notify = aqr107_link_change_notify,
|
||||
},
|
||||
|
@ -137,7 +137,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
|
|||
};
|
||||
|
||||
module_phy_driver(aqr_driver);
|
||||
@@ -895,6 +989,8 @@ static struct mdio_device_id __maybe_unu
|
||||
@@ -846,6 +940,8 @@ static struct mdio_device_id __maybe_unu
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
|
||||
|
|
|
@ -9,12 +9,12 @@ these protocols leads to link issues on system side.
|
|||
|
||||
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
|
||||
---
|
||||
drivers/net/phy/aquantia_main.c | 8 +++++++-
|
||||
drivers/net/phy/aquantia/aquantia_main.c | 8 +++++++-
|
||||
1 file changed, 7 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/net/phy/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia_main.c
|
||||
@@ -340,10 +340,16 @@ static int aqr_config_aneg_set_prot(stru
|
||||
--- a/drivers/net/phy/aquantia/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia/aquantia_main.c
|
||||
@@ -285,10 +285,16 @@ static int aqr_config_aneg_set_prot(stru
|
||||
phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
|
||||
aquantia_syscfg[if_type].start_rate);
|
||||
|
||||
|
|
|
@ -5,11 +5,11 @@ Subject: [PATCH] PONRTSYS-8842: aquantia: Add AQR113 driver support
|
|||
|
||||
Add a new entry for AQR113 PHY_ID
|
||||
---
|
||||
drivers/net/phy/aquantia_main.c | 10 ++++++++++
|
||||
drivers/net/phy/aquantia/aquantia_main.c | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/drivers/net/phy/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia_main.c
|
||||
--- a/drivers/net/phy/aquantia/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia/aquantia_main.c
|
||||
@@ -26,6 +26,7 @@
|
||||
#define PHY_ID_AQR813 0x31c31cb2
|
||||
#define PHY_ID_AQR112 0x03a1b662
|
||||
|
@ -18,7 +18,7 @@ Add a new entry for AQR113 PHY_ID
|
|||
|
||||
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
|
||||
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
|
||||
@@ -981,6 +982,14 @@ static struct phy_driver aqr_driver[] =
|
||||
@@ -932,6 +933,14 @@ static struct phy_driver aqr_driver[] =
|
||||
.get_strings = aqr107_get_strings,
|
||||
.get_stats = aqr107_get_stats,
|
||||
},
|
||||
|
@ -33,7 +33,7 @@ Add a new entry for AQR113 PHY_ID
|
|||
};
|
||||
|
||||
module_phy_driver(aqr_driver);
|
||||
@@ -997,6 +1006,7 @@ static struct mdio_device_id __maybe_unu
|
||||
@@ -948,6 +957,7 @@ static struct mdio_device_id __maybe_unu
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
|
||||
|
|
|
@ -7,11 +7,11 @@ As advised by Ian Chang this PHY is used in Puzzle devices.
|
|||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/net/phy/aquantia_main.c | 10 ++++++++++
|
||||
drivers/net/phy/aquantia/aquantia_main.c | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/drivers/net/phy/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia_main.c
|
||||
--- a/drivers/net/phy/aquantia/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia/aquantia_main.c
|
||||
@@ -27,6 +27,8 @@
|
||||
#define PHY_ID_AQR112 0x03a1b662
|
||||
#define PHY_ID_AQR412 0x03a1b712
|
||||
|
@ -21,7 +21,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
|||
|
||||
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
|
||||
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
|
||||
@@ -990,6 +992,30 @@ static struct phy_driver aqr_driver[] =
|
||||
@@ -941,6 +943,30 @@ static struct phy_driver aqr_driver[] =
|
||||
.handle_interrupt = aqr_handle_interrupt,
|
||||
.read_status = aqr107_read_status,
|
||||
},
|
||||
|
@ -52,7 +52,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
|||
};
|
||||
|
||||
module_phy_driver(aqr_driver);
|
||||
@@ -1007,6 +1033,8 @@ static struct mdio_device_id __maybe_unu
|
||||
@@ -958,6 +984,8 @@ static struct mdio_device_id __maybe_unu
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
|
||||
|
|
|
@ -10,8 +10,8 @@ This is a 5GbE chip but it reports support for 10G. Implement config_init()
|
|||
to set max speed to 5G.
|
||||
|
||||
Signed-off-by: Thomas Kupper <thomas.kupper@gmail.com>
|
||||
--- a/drivers/net/phy/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia_main.c
|
||||
--- a/drivers/net/phy/aquantia/aquantia_main.c
|
||||
+++ b/drivers/net/phy/aquantia/aquantia_main.c
|
||||
@@ -24,6 +24,8 @@
|
||||
#define PHY_ID_AQR405 0x03a1b4b0
|
||||
#define PHY_ID_AQR113C 0x31c31c12
|
||||
|
@ -21,7 +21,7 @@ Signed-off-by: Thomas Kupper <thomas.kupper@gmail.com>
|
|||
#define PHY_ID_AQR112 0x03a1b662
|
||||
#define PHY_ID_AQR412 0x03a1b712
|
||||
#define PHY_ID_AQR113 0x31c31c40
|
||||
@@ -729,6 +731,34 @@ static int aqcs109_config_init(struct ph
|
||||
@@ -674,6 +676,34 @@ static int aqcs109_config_init(struct ph
|
||||
return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
|
||||
}
|
||||
|
||||
|
@ -56,7 +56,7 @@ Signed-off-by: Thomas Kupper <thomas.kupper@gmail.com>
|
|||
static void aqr107_link_change_notify(struct phy_device *phydev)
|
||||
{
|
||||
u8 fw_major, fw_minor;
|
||||
@@ -961,6 +991,42 @@ static struct phy_driver aqr_driver[] =
|
||||
@@ -912,6 +942,42 @@ static struct phy_driver aqr_driver[] =
|
||||
.link_change_notify = aqr107_link_change_notify,
|
||||
},
|
||||
{
|
||||
|
@ -99,7 +99,7 @@ Signed-off-by: Thomas Kupper <thomas.kupper@gmail.com>
|
|||
PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
|
||||
.name = "Aquantia AQR112",
|
||||
.probe = aqr107_probe,
|
||||
@@ -1030,6 +1096,8 @@ static struct mdio_device_id __maybe_unu
|
||||
@@ -981,6 +1047,8 @@ static struct mdio_device_id __maybe_unu
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
|
||||
|
|
|
@ -25,7 +25,7 @@ Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
|||
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -369,6 +369,13 @@ config AT803X_PHY
|
||||
@@ -366,6 +366,13 @@ config AT803X_PHY
|
||||
Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
|
||||
QCA8337(Internal qca8k PHY) model
|
||||
|
||||
|
@ -41,7 +41,7 @@ Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
|||
help
|
||||
--- a/drivers/net/phy/Makefile
|
||||
+++ b/drivers/net/phy/Makefile
|
||||
@@ -94,6 +94,7 @@ obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm
|
||||
@@ -90,6 +90,7 @@ obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm
|
||||
obj-$(CONFIG_NATIONAL_PHY) += national.o
|
||||
obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o
|
||||
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
|
||||
|
|
331
target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts
Normal file
331
target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts
Normal file
|
@ -0,0 +1,331 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "mt7981.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Zbtlink ZBT-Z8102AX";
|
||||
compatible = "zbtlink,zbt-z8102ax", "mediatek,mt7981";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
led-boot = &led_status_green;
|
||||
led-failsafe = &led_status_red;
|
||||
led-running = &led_status_green;
|
||||
led-upgrade = &led_status_green;
|
||||
label-mac-device = &gmac0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 loglevel=8";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
button-reset {
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
button-mesh {
|
||||
label = "mesh";
|
||||
linux,code = <BTN_0>;
|
||||
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
button-hub {
|
||||
label = "hub";
|
||||
linux,code = <BTN_1>;
|
||||
gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_status_red: red {
|
||||
label = "red:status";
|
||||
gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
};
|
||||
|
||||
led_status_green: green {
|
||||
label = "green:status";
|
||||
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
};
|
||||
|
||||
blue {
|
||||
label = "blue:status";
|
||||
gpios = <&pio 11 GPIO_ACTIVE_LOW>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
};
|
||||
|
||||
4g {
|
||||
label = "blue:4g";
|
||||
gpios = <&pio 8 GPIO_ACTIVE_LOW>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
function = LED_FUNCTION_USB;
|
||||
function-enumerator = <0>;
|
||||
};
|
||||
|
||||
4g2 {
|
||||
label = "blue:4g2";
|
||||
gpios = <&pio 14 GPIO_ACTIVE_LOW>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
function = LED_FUNCTION_USB;
|
||||
function-enumerator = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "linux,wdt-gpio";
|
||||
gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
|
||||
hw_algo = "toggle";
|
||||
hw_margin_ms = <1000>;
|
||||
};
|
||||
|
||||
gpio-export {
|
||||
compatible = "gpio-export";
|
||||
#size-cells = <0>;
|
||||
|
||||
pcie {
|
||||
gpio-export,name = "pcie_power";
|
||||
gpio-export,output = <1>;
|
||||
gpios = <&pio 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
5g1 {
|
||||
gpio-export,name = "5g1";
|
||||
gpio-export,output = <1>;
|
||||
gpios = <&pio 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
5g2 {
|
||||
gpio-export,name = "5g2";
|
||||
gpio-export,output = <1>;
|
||||
gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sim1 {
|
||||
gpio-export,name = "sim1";
|
||||
gpio-export,output = <1>;
|
||||
gpios = <&pio 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sim2 {
|
||||
gpio-export,name = "sim2";
|
||||
gpio-export,output = <1>;
|
||||
gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
|
||||
gmac0: mac@0 {
|
||||
/* LAN */
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
nvmem-cell-names = "mac-address";
|
||||
nvmem-cells = <&macaddr_factory_4 2>;
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: mac@1 {
|
||||
/* WAN */
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&int_gbe_phy>;
|
||||
|
||||
nvmem-cell-names = "mac-address";
|
||||
nvmem-cells = <&macaddr_factory_4 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio_bus {
|
||||
switch: switch@1f {
|
||||
compatible = "mediatek,mt7531";
|
||||
reg = <0x1f>;
|
||||
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_flash_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi_nand@0 {
|
||||
compatible = "spi-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
|
||||
spi-max-frequency = <52000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
mediatek,nmbm;
|
||||
mediatek,bmt-max-ratio = <1>;
|
||||
mediatek,bmt-max-reserved-blocks = <64>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "bl2";
|
||||
reg = <0x0000000 0x0100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x100000 0x80000>;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "Factory";
|
||||
reg = <0x180000 0x200000>;
|
||||
read-only;
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
eeprom_factory: eeprom@0 {
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
|
||||
macaddr_factory_4: macaddr@4 {
|
||||
compatible = "mac-base";
|
||||
reg = <0x4 0x6>;
|
||||
#nvmem-cell-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
partition@380000 {
|
||||
label = "FIP";
|
||||
reg = <0x380000 0x200000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@580000 {
|
||||
label = "ubi";
|
||||
reg = <0x580000 0x4000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pio {
|
||||
spi0_flash_pins: spi0-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi0", "spi0_wp_hold";
|
||||
};
|
||||
|
||||
conf-pu {
|
||||
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up = <103>;
|
||||
};
|
||||
|
||||
conf-pd {
|
||||
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
|
||||
drive-strength = <8>;
|
||||
bias-pull-down = <103>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
nvmem-cells = <&eeprom_factory>;
|
||||
nvmem-cell-names = "eeprom";
|
||||
};
|
|
@ -21,7 +21,8 @@ mediatek_setup_interfaces()
|
|||
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 game" eth1
|
||||
;;
|
||||
asus,tuf-ax4200|\
|
||||
mediatek,mt7981-rfb)
|
||||
mediatek,mt7981-rfb|\
|
||||
zbtlink,zbt-z8102ax)
|
||||
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1
|
||||
;;
|
||||
asus,tuf-ax6000)
|
||||
|
|
|
@ -0,0 +1,19 @@
|
|||
. /lib/functions/uci-defaults.sh
|
||||
|
||||
board_config_update
|
||||
|
||||
board=$(board_name)
|
||||
|
||||
case "$board" in
|
||||
zbtlink,zbt-z8103ax)
|
||||
ucidef_add_gpio_switch "5g1" "Power 1st modem" "5g1" "1"
|
||||
ucidef_add_gpio_switch "5g2" "Power 2nd modem" "5g2" "1"
|
||||
ucidef_add_gpio_switch "pcie" "Power PCIe port" "pcie" "1"
|
||||
ucidef_add_gpio_switch "sim1" "SIM 1" "sim1" "1"
|
||||
ucidef_add_gpio_switch "sim2" "SIM 2" "sim2" "1"
|
||||
;;
|
||||
esac
|
||||
|
||||
board_config_flush
|
||||
|
||||
exit 0
|
|
@ -132,6 +132,7 @@ case "$board" in
|
|||
tplink,tl-xdr6088)
|
||||
[ "$PHYNBR" = "0" ] && get_mac_label > /sys${DEVPATH}/macaddress
|
||||
;;
|
||||
zbtlink,zbt-z8102ax|\
|
||||
zyxel,ex5601-t0)
|
||||
addr=$(mtd_get_mac_binary "Factory" 0x4)
|
||||
[ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
|
||||
|
|
|
@ -171,6 +171,8 @@ CONFIG_GENERIC_STRNLEN_USER=y
|
|||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GLOB=y
|
||||
CONFIG_GPIO_CDEV=y
|
||||
CONFIG_GPIO_WATCHDOG=y
|
||||
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
|
||||
CONFIG_GRO_CELLS=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
|
|
|
@ -189,6 +189,8 @@ CONFIG_GENERIC_STRNLEN_USER=y
|
|||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GLOB=y
|
||||
CONFIG_GPIO_CDEV=y
|
||||
CONFIG_GPIO_WATCHDOG=y
|
||||
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
|
||||
CONFIG_GRO_CELLS=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
|
|
|
@ -1010,6 +1010,23 @@ endif
|
|||
endef
|
||||
TARGET_DEVICES += xiaomi_redmi-router-ax6000-ubootmod
|
||||
|
||||
define Device/zbtlink_zbt-z8102ax
|
||||
DEVICE_VENDOR := Zbtlink
|
||||
DEVICE_MODEL := ZBT-Z8102AX
|
||||
DEVICE_DTS := mt7981b-zbtlink-zbt-z8102ax
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb-net-qmi-wwan kmod-usb-serial-option
|
||||
KERNEL_IN_UBI := 1
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
IMAGE_SIZE := 65536k
|
||||
IMAGES += factory.bin
|
||||
IMAGE/factory.bin := append-ubi | check-size $$(IMAGE_SIZE)
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += zbtlink_zbt-z8102ax
|
||||
|
||||
define Device/zyxel_ex5601-t0-stock
|
||||
DEVICE_VENDOR := Zyxel
|
||||
DEVICE_MODEL := EX5601-T0 (stock layout)
|
||||
|
|
8
target/linux/ramips/dts/mt7620a_rostelecom_rt-fl-1.dts
Normal file
8
target/linux/ramips/dts/mt7620a_rostelecom_rt-fl-1.dts
Normal file
|
@ -0,0 +1,8 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "mt7620a_sercomm_cpj.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "rostelecom,rt-fl-1", "ralink,mt7620a-soc";
|
||||
model = "Rostelecom RT-FL-1";
|
||||
};
|
8
target/linux/ramips/dts/mt7620a_rostelecom_s1010.dts
Normal file
8
target/linux/ramips/dts/mt7620a_rostelecom_s1010.dts
Normal file
|
@ -0,0 +1,8 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "mt7620a_sercomm_cpj.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "rostelecom,s1010", "ralink,mt7620a-soc";
|
||||
model = "Rostelecom S1010";
|
||||
};
|
309
target/linux/ramips/dts/mt7620a_sercomm_cpj.dtsi
Normal file
309
target/linux/ramips/dts/mt7620a_sercomm_cpj.dtsi
Normal file
|
@ -0,0 +1,309 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "mt7620a.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
label-mac-device = ðernet;
|
||||
|
||||
led-boot = &status_green;
|
||||
led-failsafe = &status_amber;
|
||||
led-running = &status_green;
|
||||
led-upgrade = &status_amber;
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
button-0 {
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <60>;
|
||||
};
|
||||
|
||||
button-1 {
|
||||
label = "wps";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <60>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status_green: led-0 {
|
||||
label = "green:status";
|
||||
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
};
|
||||
|
||||
status_amber: led-1 {
|
||||
label = "amber:status";
|
||||
gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
};
|
||||
|
||||
led-2 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_WAN;
|
||||
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led-3 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
function-enumerator = <1>;
|
||||
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led-4 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
function-enumerator = <2>;
|
||||
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led-5 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
function-enumerator = <3>;
|
||||
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led-6 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
function-enumerator = <4>;
|
||||
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led-7 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_WLAN;
|
||||
function-enumerator = <24>;
|
||||
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "phy1tpt";
|
||||
};
|
||||
};
|
||||
|
||||
virtual_flash {
|
||||
compatible = "mtd-concat";
|
||||
|
||||
devices = <&fwconcat0 &fwconcat1>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
compatible = "openwrt,uimage";
|
||||
/* sercomm krnl hdr with fw chksums */
|
||||
openwrt,offset = <0x100>;
|
||||
label = "firmware";
|
||||
reg = <0x0 0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ðernet {
|
||||
nvmem-cells = <&macaddr_label 0>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* mt7612 */
|
||||
&pcie0 {
|
||||
wifi@0,0 {
|
||||
compatible = "mediatek,mt76";
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
ieee80211-freq-limit = <5000000 6000000>;
|
||||
|
||||
nvmem-cells = <&eeprom_factory_8000>, <&macaddr_label 6>;
|
||||
nvmem-cell-names = "eeprom", "mac-address";
|
||||
|
||||
/* 5 GHz WLAN phy green led */
|
||||
led {
|
||||
led-sources = <2>;
|
||||
led-active-low;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <70000000>;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* whole flash */
|
||||
partition@0_all {
|
||||
label = "ALL";
|
||||
reg = <0x0 0x1000000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0 0x30000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@30000 {
|
||||
label = "ftd_and_bootflag";
|
||||
reg = <0x30000 0x20000>;
|
||||
};
|
||||
|
||||
partition@50000 {
|
||||
label = "Factory";
|
||||
reg = <0x50000 0x10000>;
|
||||
read-only;
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
eeprom_factory_0: eeprom@0 {
|
||||
reg = <0x0 0x200>;
|
||||
};
|
||||
|
||||
eeprom_factory_8000: eeprom@8000 {
|
||||
reg = <0x8000 0x200>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "SC Nvram(permanent data)";
|
||||
reg = <0x60000 0x10000>;
|
||||
read-only;
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
macaddr_label: macaddr@0 {
|
||||
compatible = "mac-base";
|
||||
reg = <0x0 0x6>;
|
||||
#nvmem-cell-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fwconcat0: partition@70000 {
|
||||
label = "Firmware";
|
||||
reg = <0x70000 0x790000>;
|
||||
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "Kernel";
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "RootFS";
|
||||
reg = <0x200000 0x590000>;
|
||||
};
|
||||
};
|
||||
|
||||
fwconcat1: partition@800000 {
|
||||
label = "Firmware2";
|
||||
reg = <0x800000 0x790000>;
|
||||
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "Kernel2";
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "RootFS2";
|
||||
reg = <0x200000 0x590000>;
|
||||
};
|
||||
};
|
||||
|
||||
partition@f90000 {
|
||||
label = "MAC IP";
|
||||
reg = <0xf90000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@fa0000 {
|
||||
label = "Critical Log";
|
||||
reg = <0xfa0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@fb000 {
|
||||
label = "Critical Log Bak";
|
||||
reg = <0xfb0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@fc0000 {
|
||||
label = "Xml Config";
|
||||
reg = <0xfc0000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@fe0000 {
|
||||
label = "Xml Config Bak";
|
||||
reg = <0xfe0000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&state_default {
|
||||
gpio {
|
||||
groups = "ephy", "rgmii1", "uartf", "wled";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
/* mt7620 */
|
||||
&wmac {
|
||||
nvmem-cells = <&eeprom_factory_0>, <&macaddr_label 2>;
|
||||
nvmem-cell-names = "eeprom", "mac-address";
|
||||
};
|
|
@ -23,6 +23,35 @@ define Build/sercomm-crypto
|
|||
rm -f $@.enc $@.key
|
||||
endef
|
||||
|
||||
define Build/sercomm-factory-cpj
|
||||
dd bs=$$((0x1fff00)) count=1 if=$@ of=$@.kernel conv=notrunc \
|
||||
2>/dev/null
|
||||
dd bs=$$((0x1fff00)) skip=1 if=$@ of=$@.rootfs1 conv=notrunc \
|
||||
2>/dev/null
|
||||
cp $@.rootfs1 $@.rootfs2
|
||||
$(TOPDIR)/scripts/sercomm-kernel-header.py \
|
||||
--kernel-image $@.kernel \
|
||||
--kernel-offset $(SERCOMM_KERNEL_OFFSET) \
|
||||
--rootfs-image $@.rootfs1 \
|
||||
--rootfs-offset $(SERCOMM_ROOTFS_OFFSET) \
|
||||
--output-header $@.header1
|
||||
$(TOPDIR)/scripts/sercomm-kernel-header.py \
|
||||
--kernel-image $@.kernel \
|
||||
--kernel-offset $(SERCOMM_KERNEL2_OFFSET) \
|
||||
--rootfs-image $@.rootfs2 \
|
||||
--rootfs-offset $(SERCOMM_ROOTFS2_OFFSET) \
|
||||
--output-header $@.header2
|
||||
cat $@.header1 $@.kernel > $@.kernel1
|
||||
cat $@.header2 $@.kernel > $@.kernel2
|
||||
rm $@.header1 $@.header2 $@.kernel
|
||||
$(call Build/sercomm-part-tag-common,kernel $@.kernel1)
|
||||
$(call Build/sercomm-part-tag-common,kernel2 $@.kernel2)
|
||||
$(call Build/sercomm-part-tag-common,rootfs $@.rootfs1)
|
||||
$(call Build/sercomm-part-tag-common,rootfs2 $@.rootfs2)
|
||||
cat $@.kernel2 $@.rootfs2 $@.kernel1 $@.rootfs1 > $@
|
||||
rm $@.kernel1 $@.rootfs1 $@.kernel2 $@.rootfs2
|
||||
endef
|
||||
|
||||
define Build/sercomm-factory-cqr
|
||||
$(TOPDIR)/scripts/sercomm-pid.py \
|
||||
--hw-version $(SERCOMM_HWVER) \
|
||||
|
@ -38,10 +67,6 @@ define Build/sercomm-factory-cqr
|
|||
mv $@.fhdr $@
|
||||
endef
|
||||
|
||||
define Build/sercomm-fix-buc-pid
|
||||
printf 1 | dd seek=$$((0x13)) of=$@ bs=1 conv=notrunc 2>/dev/null
|
||||
endef
|
||||
|
||||
define Build/sercomm-kernel
|
||||
$(TOPDIR)/scripts/sercomm-kernel-header.py \
|
||||
--kernel-image $@ \
|
||||
|
@ -104,6 +129,10 @@ define Build/sercomm-payload
|
|||
rm $@.pid
|
||||
endef
|
||||
|
||||
define Build/sercomm-pid-setbit
|
||||
printf 1 | dd seek=$$(($(1))) of=$@ bs=1 conv=notrunc 2>/dev/null
|
||||
endef
|
||||
|
||||
define Build/sercomm-prepend-tagged-kernel
|
||||
$(CP) $(IMAGE_KERNEL) $(IMAGE_KERNEL).tagged
|
||||
$(call Build/sercomm-part-tag-common,$(word 1,$(1)) \
|
||||
|
@ -117,12 +146,46 @@ define Build/sercomm-reset-slot1-chksum
|
|||
dd of=$@ seek=$$((0x118)) bs=1 conv=notrunc 2>/dev/null
|
||||
endef
|
||||
|
||||
define Build/sercomm-sysupgrade-cpj
|
||||
dd bs=$$((0x1fff00)) count=1 if=$@ of=$@.kernel conv=notrunc \
|
||||
2>/dev/null
|
||||
dd bs=$$((0x1fff00)) skip=1 if=$@ of=$@.rootfs conv=notrunc \
|
||||
2>/dev/null
|
||||
$(TOPDIR)/scripts/sercomm-kernel-header.py \
|
||||
--kernel-image $@.kernel \
|
||||
--kernel-offset $(SERCOMM_KERNEL_OFFSET) \
|
||||
--rootfs-image $@.rootfs \
|
||||
--rootfs-offset $(SERCOMM_ROOTFS_OFFSET) \
|
||||
--output-header $@.header
|
||||
cat $@.header $@.kernel $@.rootfs > $@
|
||||
rm $@.header $@.kernel $@.rootfs
|
||||
endef
|
||||
|
||||
define Device/sercomm
|
||||
$(Device/nand)
|
||||
LOADER_TYPE := bin
|
||||
IMAGES += factory.img
|
||||
endef
|
||||
|
||||
define Device/sercomm_cpj
|
||||
SOC := mt7620a
|
||||
DEVICE_VENDOR := Rostelecom
|
||||
DEVICE_ALT0_VENDOR := Sercomm
|
||||
IMAGE_SIZE := 7743k
|
||||
SERCOMM_HWID := CPJ
|
||||
SERCOMM_HWVER := 10000
|
||||
SERCOMM_SWVER := 1001
|
||||
SERCOMM_KERNEL_OFFSET := 0x70100
|
||||
SERCOMM_ROOTFS_OFFSET := 0x270000
|
||||
SERCOMM_KERNEL2_OFFSET := 0x800100
|
||||
SERCOMM_ROOTFS2_OFFSET := 0xa00000
|
||||
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \
|
||||
sercomm-sysupgrade-cpj | pad-rootfs | check-size | \
|
||||
append-metadata
|
||||
ARTIFACTS := initramfs-factory.img
|
||||
DEVICE_PACKAGES := kmod-mt76x2
|
||||
endef
|
||||
|
||||
define Device/sercomm_cxx_dxx
|
||||
$(Device/sercomm)
|
||||
KERNEL_SIZE := 6144k
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
# MT7620A Profiles
|
||||
#
|
||||
|
||||
include ./common-sercomm.mk
|
||||
include ./common-tp-link.mk
|
||||
|
||||
DEVICE_VARS += DLINK_ROM_ID DLINK_FAMILY_MEMBER DLINK_FIRMWARE_SIZE DLINK_IMAGE_OFFSET
|
||||
|
@ -1113,6 +1114,27 @@ define Device/ravpower_rp-wd03
|
|||
endef
|
||||
TARGET_DEVICES += ravpower_rp-wd03
|
||||
|
||||
define Device/rostelecom_rt-fl-1
|
||||
$(Device/sercomm_cpj)
|
||||
DEVICE_MODEL := RT-FL-1
|
||||
DEVICE_ALT0_MODEL := RT-FL-1
|
||||
ARTIFACT/initramfs-factory.img := \
|
||||
append-image-stage initramfs-kernel.bin | check-size | \
|
||||
sercomm-factory-cpj | gzip | sercomm-payload | \
|
||||
sercomm-pid-setbit 0x11 | sercomm-crypto
|
||||
endef
|
||||
TARGET_DEVICES += rostelecom_rt-fl-1
|
||||
|
||||
define Device/rostelecom_s1010
|
||||
$(Device/sercomm_cpj)
|
||||
DEVICE_MODEL := S1010
|
||||
DEVICE_ALT0_MODEL := S1010.RT
|
||||
ARTIFACT/initramfs-factory.img := \
|
||||
append-image-stage initramfs-kernel.bin | check-size | \
|
||||
sercomm-factory-cpj | gzip | sercomm-payload | sercomm-crypto
|
||||
endef
|
||||
TARGET_DEVICES += rostelecom_s1010
|
||||
|
||||
define Device/sanlinking_d240
|
||||
SOC := mt7620a
|
||||
IMAGE_SIZE := 16064k
|
||||
|
|
|
@ -2674,7 +2674,7 @@ define Device/wifire_s1500-nbn
|
|||
IMAGE_SIZE := 51200k
|
||||
IMAGE/factory.img := append-kernel | sercomm-kernel-factory | \
|
||||
sercomm-reset-slot1-chksum | append-ubi | check-size | \
|
||||
sercomm-factory-cqr | sercomm-fix-buc-pid | sercomm-mkhash | \
|
||||
sercomm-factory-cqr | sercomm-pid-setbit 0x13 | sercomm-mkhash | \
|
||||
sercomm-crypto
|
||||
SERCOMM_HWID := BUC
|
||||
SERCOMM_HWVER := 10000
|
||||
|
|
|
@ -212,6 +212,14 @@ zbtlink,zbt-we826-e)
|
|||
ravpower,rp-wd03)
|
||||
ucidef_set_led_netdev "internet" "internet" "green:wifi" "eth0"
|
||||
;;
|
||||
rostelecom,rt-fl-1|\
|
||||
rostelecom,s1010)
|
||||
ucidef_set_led_switch "lan-1" "lan-1" "green:lan-1" "switch0" "0x02"
|
||||
ucidef_set_led_switch "lan-2" "lan-2" "green:lan-2" "switch0" "0x04"
|
||||
ucidef_set_led_switch "lan-3" "lan-3" "green:lan-3" "switch0" "0x08"
|
||||
ucidef_set_led_switch "lan-4" "lan-4" "green:lan-4" "switch0" "0x10"
|
||||
ucidef_set_led_switch "wan" "wan" "green:wan" "switch0" "0x01"
|
||||
;;
|
||||
tplink,archer-c2-v1)
|
||||
ucidef_set_led_switch "lan" "lan" "green:lan" "switch1" "0x1e"
|
||||
ucidef_set_led_switch "wan" "wan" "green:wan" "switch1" "0x01"
|
||||
|
|
|
@ -120,6 +120,8 @@ ramips_setup_interfaces()
|
|||
netgear,jwnr2010-v5|\
|
||||
phicomm,k2-v22.4|\
|
||||
phicomm,k2-v22.5|\
|
||||
rostelecom,rt-fl-1|\
|
||||
rostelecom,s1010|\
|
||||
trendnet,tew-810dr|\
|
||||
zbtlink,zbt-we2026)
|
||||
ucidef_add_switch "switch0" \
|
||||
|
@ -393,6 +395,11 @@ ramips_setup_macs()
|
|||
linksys,e1700)
|
||||
wan_mac=$(mtd_get_mac_ascii config WAN_MAC_ADDR)
|
||||
;;
|
||||
rostelecom,rt-fl-1|\
|
||||
rostelecom,s1010)
|
||||
label_mac=$(mtd_get_mac_binary "SC Nvram(permanent data)" 0x0)
|
||||
wan_mac=$(macaddr_add "$label_mac" 10)
|
||||
;;
|
||||
snr,cpe-w4n-mt)
|
||||
lan_mac=$(mtd_get_mac_binary Factory 0x28)
|
||||
wan_mac=$(mtd_get_mac_binary Factory 0x2e)
|
||||
|
|
|
@ -30,6 +30,14 @@ platform_do_upgrade() {
|
|||
}
|
||||
default_do_upgrade "$1"
|
||||
;;
|
||||
rostelecom,rt-fl-1|\
|
||||
rostelecom,s1010)
|
||||
idx="$(find_mtd_index ftd_and_bootflag)"
|
||||
[ -n "$idx" ] && \
|
||||
printf 0 | dd bs=1 seek=$((0x18007)) count=1 \
|
||||
of=/dev/mtdblock$idx
|
||||
default_do_upgrade "$1"
|
||||
;;
|
||||
*)
|
||||
default_do_upgrade "$1"
|
||||
;;
|
||||
|
|
|
@ -114,12 +114,14 @@
|
|||
reg = <0x1b00000 0x400000>;
|
||||
};
|
||||
partition@1f00000 {
|
||||
compatible = "nvmem-cells";
|
||||
label = "para";
|
||||
reg = <0x1f00000 0x100000>;
|
||||
read-only;
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
read-only;
|
||||
|
||||
factory_macaddr: macaddr@fdff4 {
|
||||
reg = <0xfdff4 0x6>;
|
||||
|
@ -128,6 +130,7 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
nvmem-cells = <&factory_macaddr>;
|
||||
|
|
|
@ -72,12 +72,14 @@
|
|||
reg = <0x1b00000 0x400000>;
|
||||
};
|
||||
partition@1f00000 {
|
||||
compatible = "nvmem-cells";
|
||||
label = "para";
|
||||
reg = <0x1f00000 0x100000>;
|
||||
read-only;
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
read-only;
|
||||
|
||||
factory_macaddr: macaddr@fdff4 {
|
||||
reg = <0xfdff4 0x6>;
|
||||
|
@ -86,6 +88,7 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
nvmem-cells = <&factory_macaddr>;
|
||||
|
|
|
@ -262,12 +262,14 @@
|
|||
reg = <0x1b00000 0x400000>;
|
||||
};
|
||||
partition@1f00000 {
|
||||
compatible = "nvmem-cells";
|
||||
label = "para";
|
||||
reg = <0x1f00000 0x100000>;
|
||||
read-only;
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
read-only;
|
||||
|
||||
factory_macaddr: macaddr@fdff4 {
|
||||
reg = <0xfdff4 0x6>;
|
||||
|
@ -276,6 +278,7 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
nvmem-cells = <&factory_macaddr>;
|
||||
|
|
Loading…
Reference in New Issue
Block a user